Shin Nakao

Chip scale package: "a lightly dressed LSI chip"

A new flip-chip-like package named chip scale package (CSP) has been developed. It is constructed of LSI chips, thin resin coats, and electrode balls, having no leadframe nor any bonding wires. Wiring conductor patterns were used for electrical connection between internal pads on the die and external electrode balls. Also the transfer-bumping technique was applied for inner bump formation. Finally, solder joint life when mounted onto typical boards was estimated by simulation. >

High Thermal Conduction Package Technology for Flip Chip Devices

The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descriptions of packages and results of studies are presented and discussed here.

New developed of thin plastic package with high terminal counts

A small and thin quad flat package (QFP)-type plastic package for large-scale integrated (LSI) logic devices with high pin counts has been developed. The size of the package with 252 input and output pins is 17.3 mm by 17.3 mm, and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the package are tape automated bonding (TAB) interconnection technology, which has been developed for bonding of high-terminal-count LSIs, and the molding technology, which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. >