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Dive into the research topics where Masaya Muranaka is active.

Publication


Featured researches published by Masaya Muranaka.


Japanese Journal of Applied Physics | 1998

The Analysis of the Defective Cells Induced by COP in a 0.3-micron-technology Node DRAM

Masaya Muranaka; Kazuya Makabe; Masashi Miura; Hideaki Kato; Seihachi Ide; Hidetoshi Iwai; Masao Kawamura; Yoshitaka Tadaki; Masamichi Ishihara; Toshiyuki Kaeriyama

The influence of a crystal originated pit (COP) on the deep sub-micron dynamic-random-access-memory (DRAM), was clarified by the investigation of the defective memory cells using 0.3 microns process test-element-group (TEG) which can operate as an actual DRAM. COP constrains the growth of field oxide film and leads to degradation of the isolation characteristics between the adjacent memory cells.


Journal of The Electrochemical Society | 2000

Low-cost p-/p- epitaxial silicon wafers for densely packed metal-oxide-semiconductor devices

Hirofumi Shimizu; Tomomi Satoh; Masaya Muranaka; Kazuya Makabe; Masashi Miura

Improvements of gettering actions in the prototype p - /p - thin-film silicon epitaxial wafers (1 μm thick film) have been investigated in conjunction with avoiding failures of crystal-originated particles which degraded isolation leakage between memory cells of densely packed metal-oxide-semiconductor (MOS) devices. In order to compensate for the appearance of a kink in current-voltage curves in MOS capacitors caused by undesirable impurities, an optimized gettering and evaluation method are proposed, leading to a low-cost Czochralski-grown substrate. We pinpointed the importance of the epitaxial thickness, proposing an improved type of p - /p - epitaxial wafer with a 3-5 μm thick film that is cheaper than current p - /p + epitaxial wafers. This p - /p + epitaxial wafer meets the requirements for future miniaturized devices formed on large diameter wafers (e.g., 300 mm diam wafers).


Archive | 2004

Method of deciding error rate and semiconductor integrated circuit device

Masaya Muranaka; Hideaki Kato; Yutaka Ito


Archive | 2001

Semiconductor memory device and memory system

Masaya Muranaka; Shinichi Miyatake; Yukihide Suzuki; Kanehide Kenmizaki; Makoto Morino; Tetsuya Kitame


Archive | 2001

Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip

Masaya Muranaka


Archive | 1991

Resin-encapsulated semiconductor memory device useful for single in-line packages

Yasushi Takahashi; Kazuyuki Miyazawa; Hidetoshi Iwai; Masaya Muranaka; Yoshitaka Kinoshita; Satoru Koshiba


Archive | 1989

Semiconductor memory device with low-house pads for electron beam test

Yukihide Suzuki; Masaya Muranaka; Masamichi Ishihara


Archive | 2001

Semiconductor memory device having memory cells each capable of storing three or more values

Masaya Muranaka; Yutaka Ito


Archive | 2012

Semiconductor memory system

Shoji Wada; Kanehide Kenmizaki; Masaya Muranaka; Masahiro Ogata; Hidetomo Aoyagi; Tetsuya Kitame; Masahiro Katayama; Shoji Kubono; Yukihide Suzuki; Makoto Morino; Sinichi Miyatake; Seiichi Shundo; Yoshihisa Koyama; Nobuhiko Ohno


Archive | 1995

Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor

Yasushi Takahashi; Hidetoshi Iwai; Satoshi Oguchi; Hisashi Nakamura; Hiroyuki Uchiyama; Toshitugu Takekuma; Shigetoshi Sakomura; Kazuyuki Miyazawa; Masamichi Ishihara; Ryoichi Hori; Takeshi Kizaki; Yoshihisa Koyama; Haruo; Masaya Muranaka; Hidetomo Aoyagi; Hiromi Matsuura

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