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Featured researches published by Hidetoshi Iwai.


IEEE Journal of Solid-state Circuits | 1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

Youji Idei; Katsuhiro Shimohigashi; Masakazu Aoki; Hiromasa Noda; Hidetoshi Iwai; Katsuyuki Sato; Tadashi Tachibana

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAMs is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.


international electron devices meeting | 1998

Local-field-enhancement model of DRAM retention failure

Atsushi Hiraiwa; Makoto Ogasawara; Nobuyoshi Natsuaki; Yutaka Itoh; Hidetoshi Iwai

We have developed the local-field-enhancement model of the tail component of DRAM (dynamic random access memory) retention-time distribution. The model is in excellent agreement with experiments and proposes to control not the number but the energy-level distribution of traps and to reduce the space-charge-region-field variation together with the field itself to increase the retention time.


Journal of Applied Physics | 1996

Statistical modeling of dynamic random access memory data retention characteristics

Atsushi Hiraiwa; Makoto Ogasawara; Nobuyoshi Natsuaki; Yutaka Itoh; Hidetoshi Iwai

A statistical model to investigate the distribution of dynamic random access memory data retention times is proposed. The model assumes that the retention time is determined by a junction leakage current generated at carrier traps by a Shockley–Read–Hall process, and that the trap levels are randomly distributed not only among the memory cells but also within a cell. Monte Carlo results based on the model were in excellent agreement with experimental results, which confirmed the validity of the model. An analytical expression of the retention time distribution was also derived, and proved a good approximation near the 50% cumulative probability. Based on the model, variation in the retention time distributions among samples was found to be related to different trap‐level distributions at the SiO2/Si interface.


Journal of Applied Physics | 1997

Field-effect trap-level-distribution model of dynamic random access memory data retention characteristics

Atsushi Hiraiwa; Makoto Ogasawara; Nobuyoshi Natsuaki; Yutaka Itoh; Hidetoshi Iwai

Dynamic random access memory data retention characteristics were investigated as a function of operating voltage. Based on a statistical process, called the trap-level-distribution model, which was proposed in our previous report, we further assumed that the junction leakage current by Shockley–Read–Hall process is enhanced by an electric field through the trap-assisted-tunneling process. We incorporated into the model two processes that cause variation in the electric field at the traps; the variation of electric field itself and the spatial trap distribution. By comparing the Monte Carlo and analytical calculations with the experimental results, we found that the retention time distribution is not only caused by the energy level and spatial distributions of the traps, but by the space-charge-region field distribution among the cells. A possible origin of the field distribution is the variation of dopant profile among the junctions.


Japanese Journal of Applied Physics | 1998

The Analysis of the Defective Cells Induced by COP in a 0.3-micron-technology Node DRAM

Masaya Muranaka; Kazuya Makabe; Masashi Miura; Hideaki Kato; Seihachi Ide; Hidetoshi Iwai; Masao Kawamura; Yoshitaka Tadaki; Masamichi Ishihara; Toshiyuki Kaeriyama

The influence of a crystal originated pit (COP) on the deep sub-micron dynamic-random-access-memory (DRAM), was clarified by the investigation of the defective memory cells using 0.3 microns process test-element-group (TEG) which can operate as an actual DRAM. COP constrains the growth of field oxide film and leads to degradation of the isolation characteristics between the adjacent memory cells.


Microelectronic device technology. Conference | 1997

Statistical analysis of dynamic-random-access-memory data-retention characteristics

Atsushi Hiraiwa; Makoto Ogasawara; Nobuyoshi Natsuaki; Yutaka Itoh; Hidetoshi Iwai

Charges stored in a memory cell of a dynamic random access memory are lost by the Shockley-Read-Hall (SRH) current that is generated at carrier traps in the space-charge-region (SCR) of a junction. Magnitude of the SRH current is determined by the trap levels that are distributed not only among cells, but also within a cell. This trap-level distribution causes the temperature-dependent variation in the data retention times. The SRH current is enhanced by an SCR field, and the distribution of the field among cells also increases the variation in the retention times. Variation in the number of traps, on the other hand, contributes only slightly to the retention-time distribution. From these results we find that reduction of the electric-field distribution, as well as of the average field, is important to improve the data-retention characteristics.


Archive | 2006

Data storing method of dynamic RAM and semiconductor memory device

Yutaka Ito; Hidetoshi Iwai


Archive | 1996

Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device

Youji Idei; Katsuhiro Shimohigashi; Masakazu Aoki; Hiromasa Noda; Katsuyuki Sato; Hidetoshi Iwai; Makoto Saeki; Jun Murata; Yoshitaka Tadaki; Toshihiro Sekiguchi; Osamu Tsuchiya


Archive | 1992

Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement

Toshiyuki Sakuta; Masamichi Ishihara; Kazuyuki Miyazawa; Masanori Tazunoki; Hidetoshi Iwai; Hisashi Nakamura; Yasushi Takahashi; Toshio Maeda; Hiromi Matsuura; Ryoichi Hori; Toshio Sasaki; Osamu Sakai; Hiroyuki Uchiyama; Eiji Miyamoto; Kazuyoshi Oshima; Yasuhiro Kasama


Archive | 1995

Semiconductor integrated circuit device, and process and apparatus for manufacturing the same

Hirotaka Nishizawa; Tomoyoshi Miura; Ichirou Anjou; Masamichi Ishihara; Masahiro Yamamura; Sadao Morita; Takashi Araki; Kiyoshi Inoue; Toshio Sugano; Tetsuji Kohara; Toshio Yamada; Yasushi Sekine; Yoshiaki Anata; Masakatsu Goto; Norihiko Kasai; Shinobu Takeura; Mutsuo Tsukuda; Yasunori Yamaguchi; Jiro Sawada; Hidetoshi Iwai; Seiichiro Tsukui; Tadao Kaji; Noboru Shiozawa

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