Masayoshi Sasaki

Formation of SiOF Films by Plasma-Enhanced Chemical Vapor Deposition Using (C2H5O)3SiF

A new Plasma-Enhanced Chemical Vapor Deposition (PECVD) method using (C2H5O)3SiF: tri-ethoxy-fluoro-silane as an interlayer dielectric film is proposed based on considerations of gas chemistry. RF power dependence of the film characteristics is investigated, and it is clarified that fluorine stability is improved with increasing RF power. The relative dielectric constant of the films deposited at the power of more than 700 W is about 3.5. Moisture absorption of the film formed from TEFS at 900 W is smaller than that of the SiOF film formed from C2F6 added TEOS.

A new analytical model of SRAM cell stability in low-voltage operation

A new analytical model of MOS SRAM cell stability is presented as the measure of cell stability in low-voltage operation. The model individually deals with transistor parameters together with parasitic resistance in the cell. Mutual effects of cell-parameter variation on the lower limit of supply voltage is clarified for the first time. The V/sub CCmins/ of a conventional cell and a split wordline (SWL) cell are evaluated under the consideration of fabricated cell patterns, and superiority of the SWL cell is shown. This superiority is mainly attributed to its simple layout of the MOSFETs in the cell rather than its symmetrical layout.

The impact of oxidation of channel polysilicon on the trap-density of submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFTs, especially in leakage current. Small leakage current of less than /spl minus/20 fA//spl mu/m and high on/off ratio of about 7 orders of magnitude at a drain voltage of /spl minus/3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5/spl times/10/sup 11//cm/sup 2/ to about 10/sup 10//cm/sup 2/ at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAMs in which TFT width is less than 0.5 /spl mu/m.<<ETX>>