Kurt Knorpp

A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35- mu m CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented. >

A 9 ns 16 Mb CMOS SRAM with offset reduced current sense amplifier

A 4-Mb*4 SRAM (static random access memory) with a 9-ns access time that uses a 0.35- mu m CMOS process with KrF excimer laser lithography is descibed. The 9-ns access time is achieved by using a current-mode nonequalized read data path with an offset-reduced stabilized-feedback current sense amplifier and a quadrant-organization architecture. The design includes a current-mode wired-OR 64-b*4 parallel test circuit. The typical address access time is 9 ns at a supply voltage of 3.3 V and an output load capacitance of 30 pF. Active current is 72 mA at 30 MHz under typical conditions.<<ETX>>

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.