Masayuki Hiroi

Selective epitaxial growth by UHV-CVD using Si2H6 and Cl2

The conditions under which selective epitaxial growth (SEG) is achieved in UHV-CVD with Si2H6 are determined by the amount of Si2H6 molecules being supplied, and there is a critical gas supply amount (Fc) beyond which SEG will break down and lose its selectivity. The value of Fc is itself determined by two factors, growth temperature and the material used for masking, i.e. SiO2, Si3N4. We found that this limiting factor of Fc was increased through the addition of a small amount of Cl2, and that after such addition, the resulting decrease in growth rate is minimal.

Selective heteroepitaxial growth of Si1−xGex using gas source molecular beam epitaxy

Si1−xGex heteroepitaxial layers have been grown on Si(100) surfaces by gas source molecular beam epitaxy. Si2H6 and GeH4 were used as the Si and Ge source gases, respectively. The Ge mole fraction x in the grown film was found to be controlled by the GeH4 flow rate. The growth rate decreased gradually with increasing GeH4 flow rate. Selective epitaxial growth of Si1−xGex using a SiO2 mark on a Si(100) substrate was successfully achieved.

Gas source Si-MBE

Abstract We have devised a gas source Si-MBE apparatus. Using this apparatus, we have investigated characteristic advantages of gas source Si-MBE. In gas source Si-MBE, spitting-defect-free films were obtained. B, Sb and P doping were possible using a HBO2 cell, an ionization cell and a PH3 gas doping method, respectively. Selective epitaxial growth was achieved. P- and B-doped selective epitaxial growth using gas source Si-MBE was applied to bipolar transistor fabrication. The fabricated transistor showed normal common-emitter I–V characteristics (hFE ∼ 30). Si1-xGex selective epitaxial growth was also achieved using disilane and germane source gases. This Si1-xGex selective epitaxial growth was applied to Si1-xGex/Si hetero-diode and Si1-xGex base heterojunction bipolar transistor fabrication.

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.

Intensity oscillations in reflection high-energy electron diffraction during disilane gas source molecular beam epitaxy

Reflection high‐energy electron diffraction (RHEED) intensity oscillations during growth in disilane gas source Si molecular beam epitaxy (MBE) on Si(100) and (111) surfaces were observed under low substrate temperature and high disilane flow rate conditions. As has been observed in solid source Si MBE, these oscillations included periods corresponding to periods for monolayer and bilayer growth. On Si(100) surfaces, growth rate, which was estimated from the periods of the oscillations, was limited by a reaction process whose activation energy was 47 kcal/mol. This rate limitation is thought to stem from hydrogen desorption from monohydride phase on the Si(100). On Si(111) surfaces, oscillations in specular beam intensity were clearly observed. Although clear oscillations in the 7×7 diffraction spots could not be observed because of intensity weakness of the fractional order spots under disilane exposure. At high disilane flow rates, 7×7 diffraction spots almost disappeared and only fundamental spots were...

Heterojunction bipolar transistor fabrication using Si1−xGex selective epitaxial growth by gas source silicon molecular beam epitaxy

B doping in Si1−xGex was successfully achieved using HBO2 cell in gas source Si molecular beam epitaxy (Si‐MBE). Combining this B doping method and selective epitaxial growth of Si1−xGex by gas source Si‐MBE, B‐doped Si1−xGex selective epitaxial growth was found to be possible. This B‐doped Si1−xGex selective epitaxial growth was applied to Si1−xGex/Si heterojunction diode and Si1−xGex base heterojunction bipolar transistor (HBT) fabrications. The Si1−xGex base HBT (x=0.16, 0.22, 0.31) showed higher hFE in as‐grown condition than that for a homojunction transistor. The band‐gap difference between the Si1−xGex base and the Si emitter was estimated by the temperature dependence of the collector current ratio between the HBT and the homojunction transistor.

Selective Epitaxial Growth of Si and Si1-xGex Films by Ultrahigh-Vacuum Chemical Vapor Deposition Using Si2H6 and GeH4

Aiming at the precise profile control of Si1-xGex, selective epitaxial growth (SEG) conditions and Si1-xGex growth were investigated by ultrahigh-vacuum chemical vapor deposition (UHV-CVD) using Si2H6 and GeH4. As long as the total amount of Si2H6 did not exceed the critical amount, Si- and Si1-xGex-SEG were both achieved independent of source gas flow rate and substrate temperature. The Ge fraction x of Si1-xGex could be decided by the flow rate ratio between Si2H6 and GeH4, independent of substrate temperature. Fast gas flow switching realized the formation of a Si(120 A)/Si1-xGex(69 A) strained layer superlattice at 587°C.

Etching characteristics of Si1−xGex alloy in ammoniac wet cleaning

Etching characteristics of Si1−xGex alloys in ammoniac wet cleaning (RCA cleaning) were examined. The etching rate of Si1−xGex became larger with increasing Ge ratio (X). Temperature dependence of the etching rate was studied and the etching rate was large at high temperatures. However, no obvious difference was observed in the temperature dependence of Si1−xGex etching rate at different Ge ratio (X). A surface morhology degradation after RCA cleaning was observed at high Ge ratio (X). A stoichiometry change of Si1−xGex surface after RCA cleaning was observed by x‐ray photoelectron spectroscopy (XPS). The etching rate increase and the surface morphology degradation are thought to be due to the rapid etching of Ge atoms at the top surface layer.

Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier

We verified the effect of Ti layer insertion on stress induced void formation in wide Cu lines where voids were formed under via. In order to improve adhesion property between via and underlying Cu, PVD-Ti was inserted under Ta/TaN barrier. When nominal 30 nm thick PVD-Ti layer was inserted (Ti thickness at via bottom was about 8 nm), the failure was sufficiently suppressed without degrading the electromigration resistance. In addition, the via resistance was reduced by 25% compared with conventional Ta/TaN barrier structure, while the Cu metal resistivity was unchanged by the Ti insertion.

Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication

Using a low-k porous organosilisesqueoxane film, ALCAP/sup TM/-S with k=2.1, dual hard mask (DHM) process is proposed for Cu dual damascene interconnect (DDI) formation. The porous organosilica film has very high etching rate relative to those of the hard mask (HM) and/or etch-stop materials. SiO/sub 2//SiC is one of the best combinations for the DHM, in which the lower hard mask of SiC remained after metal CMP and protects the porous film from the via-etching damage in misalignnent region between the via-hole and the buried Cu-line. Applying in-situ resist-ashing with N/sub 2//H/sub 2/ gas, 0.4 /spl mu/m-pitched dual damascene structure is successfully fabricated. Increment of the dielectric constant is suppressed within 5% (k=2.2) after the Cu-interconnect fabrication, confirming that the DHM low-damage process is applicable for the Cu DDI fabrication in ultra low-k, porous organosilica systems.