M. Tagami

Mechanical Property Control of Low-

The dielectric constant dependence of the mechanical strength and the adhesion strength is investigated using porosity-controlled low-k films, and a material parameter is clarified to suppress the chemical mechanical polishing (CMP)-related defects in Cu damascene interconnects. Mechanical strengths such as the modulus and hardness of low-k films decreased as the dielectric constant decreased. Adhesion energy between the low-k films and an upper hard-mask layer (HM) of PECVD-SiO2 strongly depends on the dielectric constant of low-k films, while adhesion energy between the low-k films and a lower etch stop layer (ES) of SiCN shows weak dependence. It was found that the adhesion energy between the upper SiO2 and the low-k film is a critical mechanical parameter for diminishing the CMP-related defects. Introducing a porous low-k film, methylsilsesquiazane (k=2.64), with high adhesion to the HM-SiO2, we successfully fabricated single damascene copper interconnects within an acceptable limit of CMP-related defects.

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High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2 /CF4 /O2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Layered Ta-nitride (LTN) barrier film, which is composed of a TaN/sub 0.1/ polycrystalline film on a Ta/sub 2/N amorphous film, is developed for MOCVD-Cu damascene interconnects. The LTN-barrier film is easily obtained by the unique power-swing-sputtering technique, in which the RF-power is changed only from low-power for Ta/sub 2/N to high-power for TaN/sub 0.1/. The MOCVD-Cu film adheres well to the top-layered TaN/sub 0.1/ polycrystalline films due to the suppression of the accumulation of fluorine (F) at the Cu/barrier interface. The bottom-layered Ta/sub 2/N amorphous film blocks Cu diffusion. The MOCVD-Cu damascene interconnects with the LTN-barrier film are estimated to maintain reliability over 10 years under the condition of in 150 /spl deg/C, 2 MV/cm.

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

A new plasma-enhanced organic monomer-vapour polymerization (plasma polymerization) method has been developed. It was used to make a divinyl siloxane bis-benzocyclobutene (DVS-BCB) polymer film for Cu dual-damascene interconnects that had high thermal stability and a low dielectric constant, k = 2.6. The method consists of the vaporization of organic monomers, transportation of monomers in the gas phase, and polymerization by plasma to make the polymer film. The method eliminates polymer oxidation of DVS-BCB during the polymerization in high vacuum, which improves the films thermal stability. The thermal stability of plasma-polymerized BCB (p-BCB) exceeded 400°C because of the higher deposition temperature, and the film had a high resistance to Cu diffusion at 400°C annealing. The narrow-pitched Cu/BCB damascene lines showed a 35% reduction in line capacitance compared with Cu/SiO2 ones. The p-BCB is shown to be a strong candidate for Cu/low-k interconnects.

Layered Ta-nitrides (LTN) barrier film by power swing sputtering (PSS) technique for MOCVD-Cu damascene interconnects

Highly-reliable Cu interconnects with Ru/Ti barrier metal have been developed, in which Ti is diffused into the Ru-layer to establish a Cu-diffusion barrier. The PVD-Ru/Ti barrier metal with preferable crystal-orientation to Cu texture achieves the low line resistance. The Ti-doping in the Cu grain boundary just under the via improves the Cu-via reliabilities, besides keeping the Cu line resistance low. The Cu line with the Ru/Ti barrier metal is a strong candidate for automotive LSIs in future, requiring high performance and ultra-high reliability.

Highly thermal-stable, plasma-polymerized BCB polymer film

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O 2-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond

Highly-Reliable Low-Resistance Cu Interconnects with PVD-Ru/Ti Barrier Metal toward Automotive LSIs

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film

Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 /spl mu/m minimum via size) resulting in a via resistance about 0.7 /spl Omega/. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 /spl mu/m gate width. The propagation delay per inverter, which had an interconnect with 10/sup 4/ vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique.