Keizo Kinoshita

A 90nm 12ns 32Mb 2T1MTJ MRAM

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cells static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJs cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales.

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of todays VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.

Reactive ion etching of Fe-Si-Al alloy for thin film head

Elevated-temperature reactive ion etching (ET-RIE) in CCI/sub 4/ containing a gas plasma was investigated on Fe-Si-Al alloy by using an infrared lamp. A high etching rate, 200 nm/min, is obtained at 378 degrees C. Etching residues containing chloride are easily removed by an after-treatment process. Applying this ET-RIE to Fe-Si-Al alloy, a 1.7 mu m*3 mu m cross section pattern is achieved. No permeability deterioration is detected after ET-RIE. The ET-RIE method is very promising for patterning Fe-based alloy as thin-film head pole material. >

Comprehensive study of CoFeB-MgO magnetic tunnel junction characteristics with single- and double-interface scaling down to 1X nm

We study characteristics of CoFeB-MgO magnetic tunnel junction with perpendicular easy-axis (p-MTJ) at a reduced dimension down to 1X nm fabricated by hard-mask process. CoFeB-MgO p-MTJ with double-interface shows higher thermal stability down to 1X nm than that with single-interface. Thermal stability factor of 58 and intrinsic critical current of 24 μA are obtained in the CoFeB-MgO magnetic tunnel junction with perpendicular easy-axis using double-interface structure at a diameter of 20 nmφ.

Influence of CMP Chemicals on the Properties of Porous Silica Low-k Films

This paper describes the influence of the chemical mechanical polishing (CMP) process on the degradation in the leakage currents and dielectric constants of porous silica low-k films. It is found that the leakage current and dielectric constant increased by post-CMP cleaning solution due to the increase of CH x and OH bonds according to Fourier transform infrared (FTIR) absorption. This is because the surfactant in the post-CMP cleaning solution permeated into the porous silica. The permeated surfactant in the porous silica can be removed by rinsing with 2-propanol or ethanol after the CMP process. Degradations of the leakage current density and dielectric constant can be recovered by ethanol rinse and subsequent 1,3,5,7-tetramethyl-cyclo-tetrasiloxane vapor treatment, which makes the pore wall surfaces hydrophobic.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

High-speed capability and excellent reliability of a magnetic domain wall (DW) motion device required for embedded memory and logic-in-memory applications were achieved by optimizing the film stack structure of Co/Ni wire. Low-current with high-speed writing, high heat resistance, low error rate, wide operation range for temperature and magnetic field, high retention, and high endurance features were confirmed.

Etching Magnetic Tunnel Junction with Metal Etchers

Etch performances of inductory-coupled plasma (ICP) metal etchers with several gas systems are examined under constant ion energy condition to evaluate extendibility to the 300 mm wafer magnetic tunnel junction (MTJ) etch process. The ICP-Ar sputter etch affects little on magnetic properties, and shows about the same magnetoresistive (MR) ratio with conventional Ar ion milling. Major issue is the electrical short by redeposition. The etch uniformity over the wafer and precise etch end-point detection are important. The Cl2 addition to the ICP-Ar etch plasma shows serious pattern deformation and degradation of loop offset (Hoff). Methanol (Me-OH) etch shows slightly lower MR-ratio due to material degradation. However, better Hoff is observed probably due to the ion protection effect by thin carbon layer over the etched surface. Dilution of Me-OH with Ar improves MR ratio. Ar/Me-OH and ICP-Ar etch processes would be the candidate for 300 mm process at present.