Motofumi Saitoh

Interface defects responsible for negative-bias temperature instability in plasma-nitrided SiON/Si(100) systems

Interface defects generated by negative-bias temperature stress (NBTS) in an ultrathin plasma- nitrided SiON/Si(100) system were characterized by using D2 annealing, conductance-frequency measurements, and electron-spin resonance measurements. D2 annealing was shown to lower negative-bias temperature instability (NBTI) than H2 annealing. Interfacial Si dangling bonds (Pb1 and Pb0 centers), whose density is comparable to an increase in interface trap density, were detected in a NBTS-stressed sample. The NBTI of the plasma-nitrided SiON/Si system was thus shown to occur through Pb depassivation. Furthermore, the nitridation was shown to increase the Pb1/Pb0 density ratio and modify the Pb1 structure. Such a predominance and structural modification of Pb1 centers are presumed to increase NBTI by enhancing the Pb–H dissociation. Although we suggest that NBTS may also induce non-Pb defects, nitrogen dangling bonds do not seem to be included in them.

High-quality HfSixOy gate dielectrics fabricated by solid phase interface reaction between physical-vapor-deposited metal–Hf and SiO2 underlayer

We fabricated high-quality Hf–silicate (HfSixOy) gate dielectrics by utilizing the solid phase interface reaction between physical-vapor-deposited metal–Hf (typically 0.5nm thick) and SiO2 underlayers. Metal diffusion to the SiO2 layer increases the permittivity of the underlayer, while preservation of the initial SiO2∕Si bottom interface ensures good electrical properties of the gate dielectrics. The Hf–silicate layer remains amorphous and the poly-Si∕HfSixOy gate stack endures activation annealing at 1000°C. The interface trap density was comparable to that of conventional SiO2 dielectrics and the hysteresis of capacitance–voltage curves was as low as 4mV for a bias swing between −2 and +2.5V. Moreover, high electron mobility, equal to 89% of the universal mobility, was obtained for the high-k gate transistor.

A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.

Highly reliable HfSiON CMOSFET with phase controlled NiSi (NFET) and Ni/sub 3/Si (PFET) FUSI gate electrode

We have clarified that the Ni/Si composition of gate electrode and Hf/Si composition of HfSiON gate insulator are the important parameter to obtain suitable Vth of CMOS. The amount of Hf-Si bonds at the gate/insulator interface is key parameter to control Fermi-level pinning effect. The crystalline phase controlled full Ni-silicide gate (PC-FUSI) and 50% Hf composition HfSiON realize suitable Vth=+/-0.5V with tight distribution. Performance improvement (NFET:1.28 times and PFET:1.52 times) of PC-FUSI FET was also confirmed against poly-Si gate FET with keeping low leakage current. Sufficient long term reliability was also demonstrated through BT stress evaluation.

1.2 nm HfSiON/SiON stacked gate insulators for 65-nm-node MISFETs

We have investigated a Hf-based CMOSFET fabrication method that would enable the high performance and low gate leakage current that are required for the 65-nm-node CMOS devices. To suppress the gate leakage in a gate stack with an equivalent oxide thickness (EOT) of 1.2 nm, the upper layer of HfSiO film was thickened and nitrided. The nitridation improves the dielectric constant, allowing the use of a thicker HfSiO layer. The mobility was improved by lightly nitriding the bottom SiO2 interface layer, which suppresses the interfacial trap generation. Such techniques enabled us to achieve a good EOT vs Ig relationships. The Ig at an EOT of 1.2 nm was reduced by three orders of magnitude as compared with that with a SiO2 gate insulator. High mobilities, 87% of that of a SiO2 MOSFET for an NFET and 96% for a PFET, were also obtained.

Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks

We characterized how positive and negative bias temperature instabilities (PBTI and NBTI) occur in HfSiON gate stacks. The PBTI was confirmed to be suppressed by using amorphous (a-) HfSiON instead of crystallized (c-) HfSiON. The a-HfSiON reduced the capture cross-section and lowered the density of electron traps, which explains the suppression of the PBTI. The different trap parameters for a-HfSiON and c-HfSiON suggest that the electron traps of these structures have different origins. The PBTI of a-HfSiON gates occurred through electron trapping without generation of interface traps, while the NBTI of a-HfSiON gates occurred through generation of interface traps and positive oxide charges. Furthermore, it was found that the NBTI of a-HfSiON gates also involves electron trapping. Additionally, the subthreshold slope decreased under positive BT stress. We attribute these characteristic BTI behaviors of HfSiON gates to the influence of charge traps that are present within the HfSiON bulk.

Electron Holography Characterization of Ultra Shallow Junctions in 30-nm-Gate-Length Metal–Oxide–Semiconductor Field-Effect Transistors

We demonstrate that electron holography can be used to map the electrostatic potential in source–drain extensions (SDEs) of 30-nm-gate-length metal–oxide–semiconductor field-effect transistors (MOSFETs). To reduce specimen-preparation artifacts, which have prevented the electron holography of advanced MOSFETs, we prepared specimens using low-energy backside Ar ion milling. Our analysis revealed the potential distributions in SDEs formed by a co-implantation technique and those formed by a conventional BF2 implantation technique and showed that the potential change at the p–n junctions is more abrupt in the former. We also show that our electron holography results clearly describe the roll-off characteristics of the MOSFETs.

Strain Controlled CMOSFET with Phase Controlled Full-Silicide (PC-FUSI)/HfSiON Gate Stack Structure for 45nm-node LSTP Devices

By using Ni-FUSI/HfSiON gate structure with NiSi electrode for NFET and Ni₃Si for PFET, excellent T_inv-I_g property (T_inv:1.8 nm , I_g:7E-3 A/cm²), symmetrical V_th (+/-0.4V), high I_on:510/270 muA/mum with I_off: 100 pA/mum are achieved at L_g:45nm. These properties are suitable for 45nm-node CMOSFET for LSTP. To introduce Ni₃Si electrode for PFET, poly-Si gate electrode height optimization successfully overcomes volume expansion problem which causes Ni diffusion into Si substrate during full-silicidation process. For the precise thickness control of thin poly-Si electrode, we propose four-layered gate stack process. Channel strain measurement reveals that Ni₃Si from thin poly-Si introduces compressive strain to channel, which increases the hole mobility. It is considered that the thermal expansion coefficient mismatch between Ni₃Si and Si realizes the compressive stress compensating the tensile stress induced during silicidation. TEM observation shows connecting point between NiSi of NFET and Ni₃Si of PFET has abrupt interface, which suggests phase controlled full-silicidation (PC-FUSI) process is suitable for the further scaling down of CMOSFET for LSTP

In-situ electron holography of carrier accumulation at SiO2/InGaZnO4 interface

Electron holography cross-sectional observation was used to reveal changes in the charge carrier distribution in an electrode/SiO2/InGaZnO4 stacked structure caused by the electrode voltage application. Direct observation of the carrier distribution at the SiO2/InGaZnO4 interface was enabled by examining the potential distribution around the interface. The observation revealed that the electrode voltage induced accumulation and depletion of the carriers at the interface. The observed response of the carrier distribution to the electrode voltage was reproduced by a simulated response of the carrier distribution at an interface between SiO2 and an n-type semiconductor of 10+16 cm−3 doping concentration.

Single metal/single dielectric gate stack realizing triple effective workfunction for embedded memory application

We demonstrate midgap and band-edge effective workfunctions (EWFs) control with simple metal gate process scheme (single metal gate/single gate dielectric), using impurity-segregated NiSi2/SiON structure for embedded memory application. The application of midgap and band-edge EWF enables us to lower power consumption in SRAM and logic devices by 30% and 15% compared to poly-Si devices, respectively, due to reduced channel impurity concentration, suppressed gate depletion and high carrier mobility. These results show that NiSi2/SiON stack is one of the most promising candidates for future system on chip (SoC) devices with embedded memory.