Massoud Momeni

An analog VLSI chip emulating polarization vision of octopus retina

Biological systems provide a wealth of information which form the basis for human-made artificial systems. In this work, the visual system of Octopus is investigated and its polarization sensitivity mimicked. While in actual Octopus retina, polarization vision is mainly based on the orthogonal arrangement of its photoreceptors, our implementation uses a birefringent micropolarizer made of YVO/sub 4/ and mounted on a CMOS chip with neuromorphic circuitry to process linearly polarized light. Arranged in an 8/spl times/5 array with two photodiodes per pixel, each consuming typically 10 /spl mu/W, this circuitry mimics both the functionality of individual Octopus retina cells by computing the state of polarization and the interconnection of these cells through a bias-controllable resistive network.

Influence of circuit nonidealities on switched-capacitor resonators

Two different approaches exist to implement the resonators needed by a switched-capacitor (SC) bandpass modulator. Both methods use a negative feedback loop around two elements. In the first approach, these elements are SC integrators, and, in the other approach, they are implemented with SC delay cells. In this paper, the impact of nonideal circuit behavior, finite opamp gain, finite unity-gain bandwidth, and nonzero input capacitance, on the center frequency and quality factor of these resonators is analyzed and simulated when used at fs/n.

A novel leakage-estimation method for input-vector control

Input-vector control (IVC) can be used to reduce the static power dissipation of circuits or subcircuits that are idle. In actual microprocessors, many functional units are included multiple times and not in use continuously (e.g. multiplier, ALU) dissipating static and dynamic power. As the static power dissipation depends on the actual input state, IVC can be used to apply the optimal input vector (IV) that causes the lowest static power dissipation in case the unit under consideration is idle. In order to find the optimal input vector, time-consuming simulations for all possible input vectors are inappropriate for actual circuits with data-width of more than 32 bit. Statistical approaches only include a subset of all possible input vectors and are able to finish in acceptable time, but may miss the optimal input vector. In this paper, we introduce a method that qualitatively estimates the static power dissipation in a very fast way such that all possible input vectors are taken into account without requiring time-consuming computations. The Method has been validated experimentally using a 90 nm technologies.

Impact of circuit nonidealities on the implementation of switched-capacitor resonators

High-speed bandpass DeltaSigma modulation is desired in applications that require analog-to-digital conversion of narrowband signals centered around intermediate frequencies. Two different approaches exist to implement the resonators needed by a switched-capacitor (SC) bandpass modulator. Both methods use a negative feedback loop around two elements. In the first approach, these elements are SC integrators, and, in the other approach, they are implemented with SC delay cells. In this paper, the impact of nonideal circuit behavior on the center frequency and quality factor of these resonators is analyzed and simulated when used at fs/n. The nonidealities considered are finite operational amplifier gain, finite unity-gain bandwidth, and nonzero input capacitance.

A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep sub-micron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput

High-performance floating-point VLSI architecture of a lifting-based wavelet processor

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on NxM PEs which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, floating-point arithmetics are used to compute the transformation. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 2times8 PEs in a 0.18-mum technology is 4.8 mm square and the estimated operating frequency is 308 MHz.

High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs). Our architecture is based on processing elements which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, IEEE 754 floating-point arithmetics are used to compute the transformation. We also consider the normalization step which takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 8 processing elements and 2 times 256 words memory in a 0.18-mum technology is 2.2 mm2 and the estimated operating frequency is 340 MHz.