Massoud Tohidian

High-swing class-C VCO

By removing the tail current source of a class-C VCO, a high-swing VCO core has been introduced. The use of a transformer has added an additional degree of freedom so that a bias control circuit can adjust gate bias of the switching pair to a low voltage for the highest tank swing. High efficiency of class-C operation combined with high output swing led to a first class phase noise performance. The VCO oscillating at 5.11GHz, draws 1.44mA from a 0.6V power supply. The measured phase noise is −127dBc/Hz at 3MHz offset frequency resulting in a FoM of 192.3dB.

Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/√Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm2.

3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

Since the invention of radio, superheterodyne has been the architecture of choice for receivers (RX). Thanks to its high intermediate-frequency (IF), the problems related to flicker noise, time-varying dc offsets, in-band LO leakage and sensitivity to 2nd-order intermodulation are simply avoided. Unfortunately, the high IF requires high-quality-factor (Q) band-pass filters for image rejection, which cannot be easily integrated in CMOS. This forced the CMOS receivers to migrate to zero (or low) IF and suffer from the abovementioned problems. Recently, there have been attempts to revisit the high IF operation by exploiting N-path filtering [1] and a combination of a discrete-time (DT) band-pass charge-sharing filtering with feedback filtering [2]. Here, we propose a superheterodyne RX architecture with full DT operation using only gm stages, switches and capacitors. The transfer function is accurate and controlled by the clock frequency and precise capacitor ratios.

A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS

Filters are key building blocks in wireless communication and analog signal processing. Typically, Gm-C and active-RC topologies are being used for this purpose. However, reduced supply voltage and lower transistor output impedance make it difficult to implement high-gain wide-bandwidth opamps in a power-efficient manner. Moreover, portable wireless communication devices demand nowadays ever decreasing power consumption, and more tunability/reprogrammability. A discrete-time (DT) analog signal processing approach appears to answer these requirements.

Dual-core high-swing class-C oscillator with ultra-low phase noise

We propose an ultra-low phase noise oscillator topology that works on the premise that coupling a second identical oscillator core would reduce the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to achieve the lowest phase noise. The realized oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from 4.07 GHz carrier. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications.

Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise

In this paper, we exploit an idea of coupling multiple oscillators to reduce phase noise (PN) to beyond the limit of what has been practically achievable so far in a bulk CMOS technology. We then apply it to demonstrate for the first time an RF oscillator that meets the most stringent PN requirements of cellular basestation receivers while abiding by the process technology reliability rules. The oscillator is realized in digital 65-nm CMOS as a dualcore LC-tank oscillator based on a high-swing class-C topology. It is tunable within 4.07-4.91 GHz, while drawing 39-59 mA from a 2.15 V power supply. The measured PN is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from a 4.07 GHz carrier, which makes it the lowest reported normalized PN of an integrated CMOS oscillator. Straightforward expressions for PN and interconnect resistance between the cores are derived and verified against circuit simulations and measurements. Analysis and simulations show that the interconnect resistance is not critical even with a 1% mismatch between the cores. This approach can be extended to a higher number of cores and achieve an arbitrary reduction in PN at the cost of the power and area.

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.

A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection

In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1-2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8-14 dBm, while drawing only 22-40 mW in various operating modes.

Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers

A complex quadrature charge-sharing (CS) technique is proposed to implement a discrete-time band-pass filter (BPF) with a programmable bandwidth of 20-100 MHz. The BPF is part of a cellular superheterodyne receiver and completely determines the receiver frequency selectivity. It operates at the full sampling rate of up to 5.2 GHz corresponding to the 1.2 GHz RF input frequency, thus making it free from any aliasing or replicas in its transfer function. Furthermore, the advantage of CS-BPF over other band-pass filters such as N-path, active-RC, Gm-C, and biquad is described. A mathematical noise analysis of the CS-BPF and the comparison of simulations and calculations are presented. The entire 65 nm CMOS receiver, which does not include a front-end LNTA for test reasons, achieves a total gain of 35 dB, IRN of 1.5 nV/√(Hz), out-of-band IIP3 of +10 dBm. It consumes 24 mA at 1.2 V power supply.

A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF

We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47 mm2 of active area and consumes 24.5 mA at 1.2V power supply.