R. Bogdan Staszewski

A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations

Base-station (BTS) RX oscillator phase noise requirements between 600kHz and 3MHz are difficult to satisfy using a fully monolithic VCO fabricated in bulk-CMOS technology. The GSM-900-BTS and the DCS-1800-BTS RX specifications at 800kHz of -147dBc/Hz and -138dBc/Hz, respectively, are considered the most difficult to meet. In GSM mobile stations (MS), the transmit and receive bands are 20MHz apart, which sets a stringent TX phase noise requirement of -162dBc/Hz at 20MHz offset [1]. A VCO satisfying this inadvertently meets the relatively relaxed RX specification.

A mm-Wave FMCW radar transmitter based on a multirate ADPLL

We present a 60-GHz FMCW radar transmitter based on an all-digital phase-locked loop (ADPLL) with ultra-wide linear frequency modulation. Multirate, two-point modulation generates an ultra-linear programmable frequency ramp. A novel, closed-loop DCO gain linearization method employing 24kb of SRAM realizes a GHz-level triangular chirp with high sweep linearity, and enables hitless modulation through multiple DCO tuning banks. Measured frequency error (i.e., nonlinearity) in the FMCW ramp is only 117-kHzrms for a 62-GHz carrier with 1.22-GHz bandwidth. The synthesizer is transformercoupled to a 3-stage neutralized power amplifier that delivers +5 dBm to a 50-Ω load. Implemented in 65-nm CMOS, the transmitter prototype consumes 89 mW from a 1.2-V supply.

High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators

Mm-wave digitally-controlled oscillators (DCOs) with reconfigurable passive resonators are proposed, which achieve wide tuning range (>;10%) and fine frequency resolution (<;1 MHz) simultaneously. Two 60-GHz implementations: a fine-resolution inductor-based DCO (L-DCO) and a transformer-based DCO (T-DCO) are demonstrated in 90-nm CMOS, exploiting metal capacitors only for frequency tuning. Both DCOs obtain >;9.7% linear tuning range and phase noise lower than -90.5 dBc/Hz at 1-MHz offset across the 56-62 GHz range. The T-DCO achieves fine frequency tuning step of 2.5 MHz, whereas that of the L-DCO is better than 160 kHz. The L-DCO and T-DCO consume 10 mA and 12 mA, respectively, from a 1.2-V supply. The core size of each DCO is 0.4×0.4 mm2.

An EDGE transmitter with mitigation of oscillator pulling

We propose a polar transmitter architecture that is robust to modulation-induced injection pulling of its RF oscillator by means of a built-in self compensation. A mathematical model is presented for the injection pulling mechanism, which incorporates a digitally-controlled delay circuit that minimizes injection pulling by adjusting the overall phase shift in the parasitic path between the final amplitude modulation stage (aggressor) and the RF oscillator (victim). The technique is verified in a 65-nm CMOS GSM/GPRS/EDGE SoC demonstrating compliant error vector magnitude (EVM) and modulation spectral-mask performance over process and temperature.

A highly selective LNTA capable of large-signal handling for RF receiver front-ends

To achieve ultimately flexible multi-core radio operation, wide-band receiver RF front-ends must be robust against interference well in excess of the requirements usually specified by a radio standard. In this paper, a highly selective, very linear low-noise transconductance amplifier (LNTA) capable of large-signal handling for current-mode receiver (RX) front-ends is proposed and implemented in 65-nm CMOS. It is shown that by combining on-chip highQ bandpass filters with a push/pull class-AB common-gate stage, a measured 1-dB desensitization point (B1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved. In addition, by applying a noise cancellation technique, via an auxiliary push/pull class-AB common-source stage, the proposed LNTA measures a moderate NF of 5.9 dB, which is a very competitive number for such high value of B1dB. The circuit consumes 7.5 mA at 1.5 V.

Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS

WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and high band, respectively. A key component of the ADPLL is a time-to-digital converter (TDC), which replaces the traditional phase/frequency detector and charge-pump. The TDC implementation in 40-nm CMOS technology is chosen and presented in this paper. The TDC architecture is based on a pseudo-differential structure. The TDC system has been verified at 1.2 V of power supply, 33.868 MHz frequency reference (FREF) clock and 4.25 GHz output RF frequency. It is found that the power consumption is about 2.99 mW without a clock gating scheme, but is expected to be reduced to 0.78 mW with the clock gating scheme. The INL and DNL of the TDC is lower than 0.4 LSB. The TDC resolution is between 10.84–12.55 ps. At the worst case condition, the TDC resolution of 12.55 ps will produce the in-band phase noise better than −95 dBc/Hz as required by WiMAX ADPLL system. The TDC core layout has a silicon area of only 125×11 µm2.

A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF

We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47 mm2 of active area and consumes 24.5 mA at 1.2V power supply.

A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS

A SAW-less discrete-time superheterodyne receiver (RX) with multi-stage harmonic rejection in 28nm CMOS, featuring highly linear LNTA, employs a novel blocker-resilient octal charge-sharing band-pass filter to achieve low power consumption. The RX features NF of 2.1 to 2.6 dB, and IIP3 of 8 to 14 dBm, while drawing only 24 to 37 mW in different operating modes.

Frequency translation through fractional division for a two-channel pulling mitigation

We present a two-channel RF generation system for a 2 GHz basestation transmitter that avoids pulling due to various parasitic coupling paths, especially between a strong RF output and a sensitive LC-tank of an RF oscillator. This is achieved through a fractional frequency translation by means of a programmable fractional divider realized as a dynamic edge selector of eight oscillator phases. This way, the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels is avoided, thus rendered harmless in the creation of injection pulling spurs. The proposed method can push the injection pulling spurs far away from the carrier and at an infinitesimal power level below -80 dBc. The pulling mitigation for two RF channels has been verified in a 65-nm CMOS testchip that occupies 0.56×1.46 mm2 area and emits -156 dBc/Hz noise floor. An RF oscillator is realized as a class-C topology without tail current source.

Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitters wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.