Masuri Othman

High performance parallel multiplier using Wallace-Booth algorithm

This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix/spl I.bar/4 modified Booth algorithm and the Wallace Tree structure. The design is structured for a n/spl times/m multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2. To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands. An efficient VHDL code was written and successfully simulated and synthesised using Alteras MaxplusII(10.0) and ModelSim3.4 CAD tools.

Development of a Fuzzy Logic Controller Algorithm for Air-conditioning System

The goal of this paper is to develop an algorithm of fuzzy logic controller (FLC) for automatic air-condition controlling system. The fuzzy logic system is used to design this algorithm. Two inputs and one output are designed with an industrial application in mind. This system consists of two sensors for feedback control: one to the monitor of temperature and another one to the monitor of humidity. There are three control elements: cooling valve, heating valve, and humidifying valve, to adjust the temperature and humidity of the air supply. Fuzzy rules are formulated by temperature and humidity. The model of this controller algorithm has been simulated using MATLAB simulation. Finally, the developed algorithm has been designed for implementing the hardware VLSI chip using VHDL language from EDA tools.

High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm

Parallel-prefix adders offer high efficiency solution in terms of area, speed, power and regularity to the binary addition problem and are well suited for VLSI implementation. In this paper, a novel technique of implementing a hybrid parallel- prefix ling adder is presented. Experimental results show that the proposed adder has an improvement of 63% in speed and about 13% reduction in power consumption compared to Carry Lookahead adder (CLA).

On-Line DA-LUT Architecture for High-Speed High-Order Digital FIR Filters

This paper presents a new architecture for distributed arithmetic look-up table (DALUT). The technique proposed here shows a dramatic improvement in the memory size of the architecture used for implementing a high-speed high-order digital finite impulse response filter. The architecture proposed in this paper provides DA technique the cure for its major disadvantage i.e. the exponential growth of the LUT as the filter order increase. Therefore, with this architecture, the LUT size is independent of the number of input variables. This is because the LUT contents are not precalculated before implementing the design, instead the only needed location contents are calculated while processing the input data. As a result of applying this architecture, the usual drawback of the FIR filters, i.e. high order needs when compared with their corresponding IIR filters is also vanished. Therefore, with this architecture we can easily design and implement FIR filters to meet the desired specifications even if the required filter order is high

Implementation of a high speed Fast Fourier Transform VLSI chip

Abstract Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussion on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.

Chemical field-effect transistor with constant-voltage constant-current drain-source readout circuit

Response of Chemical Field-Effect Transistor (CHEMFET) electrochemical sensors are taken from the output of a readout interface circuit that maintains constant drain-source voltage and current levels. We employ the readout circuit for the purpose of supervised learning training data collection. Sample solutions are prepared by keeping the main ion concentration constant while the activity of an interfering ion varied based on the fixed interference method. Results show that the voltage response demonstrates linear relationship to the ion concentration within the detection limit. However, noise in the form of abrupt and random changes in DC levels reduces correlation and increases mean square error between similarly repeated measurements. We find that referencing the voltage response to the sensor response in DIW prior to measurement greatly improves the repeatability. The process of approximating ionic concentration level is achieved up to 80% recognition by feeding the readout circuit output to a neural network post-processing stage.

FPGA Implementation of a Canonical Signed Digit Multiplier-less based FFT Processor for Wireless Communication Applications

This paper proposes a novel fully parallel FFT architecture based on canonical signed digit (CSD) multiplier-less targeting wireless communication applications, such as IEEE802.15.3a wireless personal area network (WPAN) baseband. The proposed architecture has the advantages of high throughput, less latency, and smaller area. The multiplier-less architecture uses shift- and-add operations to realize the complex multiplier and uses the CSD to optimize these operations. The design has been coded in Verilog HDL targeting Xilinx Virtex-II FPGA series. It is fully implemented and tested on real hardware using Virtex-II FG456 prototype board. Based on this architecture, the implementation of 8-points FFT on Virtex-II can run at a maximum clock frequency of about 400 MHz which lead to about 3.2 GS/s throughput with a latency of 6 clock cycles using 16,580 equivalent gates. Comparison with a conventional parallel architecture design of the same size can run only at a maximum clock frequency of 220 MHz or 1.76 GS/s throughput with a latency of 12 clock cycles using 77,418 equivalent gates for the design. The resulting throughput increases by about 82% while the equivalent gates and latency decrease by about 79% and 50% respectively.

Improved fine CFO synchronization for MB-OFDM UWB

Proposed is an improved blind carrier frequency offset (CFO) estimator suitable for Multi-Band OFDM Ultra Wideband (MB-OFDM UWB) system. By exploiting the conjugate symmetry of the physical layer convergence protocol (PLCP) the need for training symbols can be avoided and estimation performance is improved as well. Computer simulations show that the proposed method achieves better estimation performance than existing method.

A BPSK Backscatter Modulator Design for RFID Passive Tags

An integrated circuit implementation of a BPSK backscatter modulator for passive radio frequency identification (RFID) transponders has been carried out. The design is based on a combination and modification of earlier techniques. The modulation technique that has been used in this study is binary phase shift keying (BPSK). This kind of modulator provides modulation in an ultra high frequency (UHF) wave band along with significantly low power dissipation. Furthermore, the topology of the developed modulator allows us to control its output resistance so that only a minor fraction of the active power at the antenna propagates to the modulator. In the circuit development process, the cost and the size of the modulator has also been taken into consideration. The development of the modulator circuit is simulated in computer aided design software, P-SPICE. An efficient modulator has been achieved in the UHF band after optimization of the circuit components in a carefully investigated circuit design. This design also shows the minimum power dissipation of around 7.52 times 10-11 W, as a result of optimization and minimization of the circuit size.

Design and Synthesis of Mobile Robot Controller using Fuzzy

Abstract This paper describes a Fuzzy Logic Controller (FLC) algorithm for designing an autonomous mobile robot controller (MRC). The controller enables the robot to navigate in an unstructured environment and that avoid any encountered obstacles without human intervention. The autonomous mobile robot is found to be able to react to the environment appropriately during its navigation to avoid crashing with obstacles by turning to the proper angle while moving. The Fuzzy Logic algorithm has proven a commendable solution in dealing with certain control problems when the situation is ambiguous. One of the main difficulties faced by conventional control systems is the inability to operate in a condition with incomplete and imprecise information. As the complexity of a situation increases, a traditional mathematical model will be difficult if not impossible to implement. Fuzzy Logic is a tool for modeling uncertain systems by facilitating common sense reasoning in decision-making in the absence of complete and precise information. In this paper, the controller of an autonomous mobile robot is designed based on the theories of Fuzzy Logic. The wheeled robot is able to navigate by itself in a completely unstructured environment. The codes of MRC has written for implementing the separate modules of the Fuzzifier, Fuzzy Rule Base, Inference mechanism and Defuzzifier as hardware blocks. A behavioral model of MRC algorithm is first developed in Matlab session with numerous data to evaluate its algorithm functionality. The development of Matlab codes has converted into VHDL codes for hardware implementation. Comparison resultsbetween MATLAB and VHDL of MRC algorithm also presented. Then the VHDL codes are synthesized using synthesis tool, known as Quartus II. Finally the MRC hardware blocks for VLSI design have been carried out.