Shabiul Islam

Cognitive impairment and memory dysfunction after a stroke diagnosis: a post-stroke memory assessment

Cognitive impairment and memory dysfunction following stroke diagnosis are common symptoms that significantly affect the survivors’ quality of life. Stroke patients have a high potential to develop dementia within the first year of stroke onset. Currently, efforts are being exerted to assess stroke effects on the brain, particularly in the early stages. Numerous neuropsychological assessments are being used to evaluate and differentiate cognitive impairment and dementia following stroke. This article focuses on the role of available neuropsychological assessments in detection of dementia and memory loss after stroke. This review starts with stroke types and risk factors associated with dementia development, followed by a brief description of stroke diagnosis criteria and the effects of stroke on the brain that lead to cognitive impairment and end with memory loss. This review aims to combine available neuropsychological assessments to develop a post-stroke memory assessment (PSMA) scheme based on the most recognized and available studies. The proposed PSMA is expected to assess different types of memory functionalities that are related to different parts of the brain according to stroke location. An optimal therapeutic program that would help stroke patients enjoy additional years with higher quality of life is presented.

Investigation into Mass Loading Sensitivity of Sezawa Wave Mode-Based Surface Acoustic Wave Sensors

In this work mass loading sensitivity of a Sezawa wave mode based surface acoustic wave (SAW) device is investigated through finite element method (FEM) simulation and the prospects of these devices to function as highly sensitive SAW sensors is reported. A ZnO/Si layered SAW resonator is considered for the simulation study. Initially the occurrence of Sezawa wave mode and displacement amplitude of the Rayleigh and Sezawa wave mode is studied for lower ZnO film thickness. Further, a thin film made of an arbitrary material is coated over the ZnO surface and the resonance frequency shift caused by mass loading of the film is estimated. It was observed that Sezawa wave mode shows significant sensitivity to change in mass loading and has higher sensitivity (eight times higher) than Rayleigh wave mode for the same device configuration. Further, the mass loading sensitivity was observed to be greater for a low ZnO film thickness to wavelength ratio. Accordingly, highly sensitive SAW sensors can be developed by coating a sensing medium over a layered SAW device and operating at Sezawa mode resonance frequency. The sensitivity can be increased by tuning the ZnO film thickness to wavelength ratio.

Cognitive assessments for the early diagnosis of dementia after stroke

The early detection of poststroke dementia (PSD) is important for medical practitioners to customize patient treatment programs based on cognitive consequences and disease severity progression. The aim is to diagnose and detect brain degenerative disorders as early as possible to help stroke survivors obtain early treatment benefits before significant mental impairment occurs. Neuropsychological assessments are widely used to assess cognitive decline following a stroke diagnosis. This study reviews the function of the available neuropsychological assessments in the early detection of PSD, particularly vascular dementia (VaD). The review starts from cognitive impairment and dementia prevalence, followed by PSD types and the cognitive spectrum. Finally, the most usable neuropsychological assessments to detect VaD were identified. This study was performed through a PubMed and ScienceDirect database search spanning the last 10 years with the following keywords: “post-stroke”; “dementia”; “neuro-psychological”; and “assessments”. This study focuses on assessing VaD patients on the basis of their stroke risk factors and cognitive function within the first 3 months after stroke onset. The search strategy yielded 535 articles. After application of inclusion and exclusion criteria, only five articles were considered. A manual search was performed and yielded 14 articles. Twelve articles were included in the study design and seven articles were associated with early dementia detection. This review may provide a means to identify the role of neuropsychological assessments as early PSD detection tests.

VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

The need for high performance transceiver with high Signal to Noise Ratio (SNR) has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC) for wireless transceiver. This research work presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC) filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

Design and implementation of discrete cosine transform chip for digital consumer products

This paper describes the design and implementation of a VLSI process for a DCT codec to use in digital consumer products. The design flow starts from the system specification to implementation process on silicon. The entire process is carried out using an advanced workstation based design environment for digital signal processing. To ensure that the designed VLSI processor satisfies the required specifications the software adopts the bit-true analysis. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc). The motivation behind the work is small size chip area, faster processing, and reducing the cost of the chip

Schmitt Trigger based on Dual Output Current Controlled Current Conveyor in 16nm CMOS technology for digital applications

This paper presents a current mode Schmitt Trigger based on Dual Output Current Controlled Current Conveyor (DOCCCII). To overcome the frequency limitation and enable low voltage low power operation (LVLP) current mode circuits are generally preferred. They offer higher bandwidth, improved slew rate and better (LVLP) performance compared to their voltage mode counterparts. So for the design we have selected second generation current controlled current conveyor which is regarded as the universal current mode active building block. The circuit topology is very simple, its construction consists of a single DOCCCII and an inverter implemented in 16 nm bulk CMOS technology model parameters obtained from Predictive Technology Model (PTM) together with two resistors. The circuit is suitable for integration, it uses the supply voltage of ±0.8V and a bias current of 10μA. The performance of the proposed circuit is examined using H-Spice where the circuit exhibited the power dissipation of 57.78μW. The circuit performance is in agreement with the theoretical explanation. The noise removing capability of the circuit is presented here as an application.

Study of the side gate junctionless transistor in accumulation region

Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

Numerical investigation of channel width variation in junctionless transistors performance

Double gate junctionless (DGJLT) transistor, as a pinch off device, was previously fabricated. In this letter, the impact of channel width variation on behaviour of the device is studied by means of 3D-TCAD simulation tool. In this matter, the transfer characteristics, energy band diagram (valence/conduction band) and normal electric field along the nanowire between the source and the drain are studied at pinch off state. By decreasing the nanowire width, the on current decreases. Threshold voltage also reduced by decreasing the wire width. The highest electric field occurs at off state and the normal component of the electric field is stronger for smaller channel width. At pinch off state, the energy band diagrams revealed that a potential barrier against the current flow was built in channel which the smallest width has higher potential barrier. The overall result agrees with the behaviour of the nanowire junctionless transistors.

FPGA realization of Inverse Discrete Wavelet Transform

Lifting Scheme based 2-D Inverse Discrete Wavelet Transform 2-D (IDWT) core for JPEG 2000 is implemented into FPGA following a new approach of reusing hardware components. The approach leads towards higher area efficiency and speed optimization. Design realized by Le-Gall 5/3 filter, achieved significant acceleration that executes at over 300MHz with 7.13Msamples throughput whereas using less than 1% of logic elements in Altera Stratix II FPGA. High quality reconstructed image are extracted from Matlab and VHDL simulations. Implementation details of the individual hardware blocks, synthesis result, and performance analysis are presented.

A simulation study of thickness effect in performance of double lateral gate junctionless transistors

The electrical behaviour of double lateral gate junctionless transistors, regarding to the variation of channel thickness is investigated, through 3-D numerical simulations. The simulation results explicitly show that how the device thickness affect the on and off current and threshold voltage behavior based on variation of the carriers density and recombination rates of the carriers. As the channel thickness is decreased, the amount of bulk neutral channel getting smaller which cause a decrease in the on state current. Meanwhile, the lateral gate influence on the channel is reinforced, which cause a decrease in leakage current in the off state. Threshold voltage is decreased as the channel thickness decreases. However, the recombination rate of carriers increases with decreasing the channel thickness, due to the accumulation of minority carries and shifted to the source side of the channel.