Matteo Bassi

An Integrated Microwave Imaging Radar With Planar Antennas for Breast Cancer Detection

The system design of an integrated microwave imaging radar for the diagnostic screening of breasts cancer is presented. A custom integrated circuit implemented in a 65-nm CMOS technology and a pair of patch antennas realized on a planar laminate are proposed as the basic module of the imaging antenna array. The radar operates on the broad frequency range from 2 to 16 GHz with a dynamic range of 107 dB. Imaging experiments carried out on a realistic breast phantom show that the system is capable of detecting tumor targets with a resolution of 3 mm.

Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints

We present a behavioral analysis of two different transceiver architectures for UWB breast cancer imaging employing a SFCW radar system. A mathematical model of the direct conversion and super heterodyne architectures together with a numerical breast phantom are developed. FDTD simulations data are used on the behavioral model to investigate the limits of both architectures from a circuit-level point of view. Insight is given into I/Q phase inaccuracies and their impact on the quality of the final reconstructed images. The result is that the simplicity of the direct conversion makes the receiver more robust towards the critical circuit impairments for this application, that is the random phase mismatches between the TX and RX local oscillators.

A 40–67 GHz Power Amplifier With 13 dBm

Pushed by the availability of large fractional bandwidths, many well-established applications are focusing mm-wave spectrum for product deployment. Generation of broadband power at mm-waves is challenging because a key target such as the efficiency trades with the gain-bandwidth (GBW) product. The major limit is the capacitive parasitics at the interstage between driver and power devices. The latter are designed with a large form factor so as to deliver the desired output power and are commonly biased in class-AB to achieve high drain efficiency, penalizing GBW. In this paper, a design methodology for interstage and output matching networks targeting large fractional bandwidth and high efficiency is proposed. Leveraging inductively coupled resonators, we apply Norton transformations for impedance scaling. In both networks, topological transformations are employed to include a transformer, achieve the desired load impedance and minimize the number of components. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output power over the 40-67 GHz bandwidth with a peak power-added efficiency of 16% without power combining. To the best of authors knowledge, the presented PA shows state-of-the-art performances with the largest fractional bandwidth among bulk CMOS mm-wave PAs reported so far.

{\rm P}_{\rm SAT}

The development of next-generation electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore their minimum speed. As such, aggregation of currently available 25Gb/s systems is not an option, and the migration path requires serial interfaces to operate at increased rates. According to CEI-56G and IEEE P802.3bs emerging standards, PAM-4 signaling paired to forward error correction (FEC) schemes is enabling several interconnect applications and low-loss profiles [1]. Since the amplitude of each eye is reduced by a factor of 3, while noise power is only halved, a high transmitter (TX) output amplitude is key to preserve high SNR. However, compared to NRZ, the design of a PAM-4 TX is challenged by tight linearity constraints, required to minimize the amplitude distortion among the 4 levels [1]. In principle, current-mode (CM) drivers can deliver a differential peak-to-peak swing up to 4/3(VDD-VOV), but they struggle to generate high-swing PAM-4 levels with the required linearity. This is confirmed by recently published CM PAM-4 drivers, showing limited output swings even with VDD raised to 1.5V [2-4]. Source-series terminated (SST) drivers naturally feature better linearity and represent a valid alternative, but the maximum differential peak-to-peak swing is bounded to VDD only. In [5], a dual-mode SST driver supporting NRZ/PAM-4 was presented, but without FFE for PAM-4 mode. In this paper, we present a PAM-4 transmitter leveraging a hybrid combination of SST and CM driver. The CM part enhances the output swing by 30% beyond the theoretical limit of a conventional SST implementation, while being calibrated to maintain the desired linearity level. A 5b 4-tap FIR filter, where equalization tuning can be controlled independently from output matching, is also embedded. The transmitter, implemented in 28nm CMOS FDSOI, incorporates a half-rate serializer, duty-cycle correction (DCC), ≫2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s while drawing 120mA from a 1V supply. The power efficiency is ~2 times better than those compared in this paper.

and 16% PAE in 28 nm CMOS LP

A continuous-time 7-tap FIR equalizer tailored to dispersion compensation in multi-mode fiber links is presented. By using a novel active delay line, the ultra-compact equalizer is very flexible, maintaining optimal performances and power scalability over a wide range of input data-rates. Particular care is taken to address critical issues of continuous-time realizations, such as noise, linearity and dynamic range. All-pass stages, realized with a simple circuit topology featuring high linearity and wide bandwidth, are investigated to implement the active delay line elements. Filter tap coefficients are realized with programmable transconductors and output currents are summed through a transimpedance amplifier, providing simultaneously high gain and wide bandwidth. Extensive experimental results, carried out on test chips realized in 28 nm LP CMOS technology, are presented. The equalizer demonstrates successful operation with variable data-rates ranging from 10 Gb/s to 25 Gb/s and power dissipation scalable from 55 mW to 90 mW. Compared to previously reported high-speed FIR equalizers, the proposed solution accepts the largest variation of the input data-rate with state-of-the-art power efficiency and core silicon area of only 0.085 mm 2, meeting the demand of emerging 400 Gb/s standards.

3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

A 65-nm CMOS receiver tailored for breast cancer diagnostic imaging is demonstrated for the first time. The receiver shows 31-dB conversion gain, NF <; 8.6 dB , P1 dB > -28 dBm, IIP3 > -12 dBm and IIP2 > 22 dBm over a band from 1.75 to 15 GHz. A programmable injection-locked divider generates quadrature LO signals with a I/Q phase error <; 1.5 ° over three octaves without requiring any calibration or tuning. The receiver shows a flicker noise corner as low as 40 Hz, achieving a dynamic range of 106 dB.

Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS

Pushed by the ever-increasing demand of high-speed connectivity, next generation 400 Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45 Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits feed-forward equalizer (FFE), and allows tuning the output impedance to ensure good source termination. Implemented in 28 nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >> 2 kV HBM ESD diodes, and delivers a full swing of 1.3 Vppd at 45 Gb/s, while drawing only 120 mA from 1 V supply. The power efficiency is ~ 2 times better than previously reported PAM-4 transmitters.

A 65-nm CMOS 1.75–15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer

A 65 nm CMOS receiver tailored for breast cancer diagnostic imaging is demonstrated for the first time. The receiver shows 31 dB conversion gain, NF<;8.6dB, PidB >;-28dBm, IIP3>;-12dBm and IIP2>;22dBm over a band from 1.75 to 15 GHz. A programmable injection-locked divider generates quadrature LO signals with a I/Q phase error <;1.5° over 3 octaves without requiring any calibration or tuning. The receiver shows a flicker noise corner as low as 40 Hz, achieving a dynamic range of 106 dB.

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI

Multi-mode fiber (MMF) is the most cost-effective fiber for high-speed LANs. Modal dispersion leads to optical-energy spreading over several symbol periods, drastically limiting distance and data-rate. Compared with copper channels, equalization is challenging because the channel response varies enormously from fiber to fiber and also over time [1]. These aspects, paired with the practical difficulty of implementing TX pulse shaping, increase the equalization burden at the receiver. To date, electronic dispersion compensation (EDC) consisting of an FIR filter cascaded with a nonlinear equalizer, such as DFE, enables 10Gb/s up to 300m according to the 10GBASE-LRM standard. To satisfy the demand for greater network capacity, solutions to reach 25Gb/s on a single fiber, and up to 400Gb/s aggregated throughput with space-division multiplexing on 16 fibers are being investigated [2]. At this data-rate, robust DSP-based EDCs still need high power, indicating an analog approach to signal processing to reduce power. To have market impact and economic feasibility, the interface must be flexible, accommodating a variable data-rates for compatibility with legacy channels and different standards [2]. In addition, achieving high energy efficiency at each standard (i.e., data rate) is fundamental.

A 1.75–15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS

Radar imaging is gaining interest for medical, security, and industrial applications. Enabled by the advances in silicon technologies, a clear trend towards higher integration is observed [1-3]. Early-stage breast cancer detection is a promising application for radar imaging, as first clinical trials with patients have been carried out [4]. Commercial VNAs have been used in these experiments, but custom hardware is needed to improve the sensitivity, and to decrease the size and the cost of the setup [4]. Medical radar imaging sets great challenges. The radiation must be coupled into the body, while the skin acts as a shield. The waves that penetrate beyond the skin are heavily attenuated (>80dB for a few centimeters at 10GHz [4]). Tumor cells have different electrical properties than the healthy tissue, thus reflecting the waves and allowing for detection; this contrast is frequency dependent, decreasing at higher frequencies. These fundamental limits result in a radar requiring a dynamic range in excess to 100dB [4], and force operation in the lower-GHz range. In contrast, mm-Waves would be preferred to achieve higher resolution [1]. Ultra-wideband radars combine larger scattered energy collected at lower frequencies (thus higher SNR), and mm-range resolution, since the resolution is set by the overall bandwidth and the antenna array arrangement [2].