Matthew Goldman

A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte/s programming

A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.

A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]

A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.