Bharat Pathak

A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

A 172mm 2 32Gb MLC NAND flash memory in 34nm CMOS

As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements [1,2]. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device that employs chip architecture, datapath, and analog architecture solutions that address these challenges while meeting high performance requirements. This 32Gb MLC NAND delivers 50µs tREAD, 900µs tPROG and 9MB/s write throughput in a 34nm technology.

A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]

A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.

A 128 Mb NOR flash memory with 3 MB/s program time and low-power write performance by using in-package inductor charge-pump

Improved performance of flash memories requires programming more cells in parallel. This design uses an inductive pump to transfer the energy to a capacitor to achieve the needed voltage. The discrete inductor is bonded atop the die which also includes the control circuitry. With an inductive pump, the current saving in the program mode is 47.5 mA compared to a capacitive pump.