Matthew J. Kay

Effect of Accumulated Charge on the Total Ionizing Dose Response of a NAND Flash Memory

Consecutive write operations performed on a Samsung NAND flash memory are shown to significantly increase the total ionizing dose level at which data corruption occurs. Consequences of multiple consecutive write operations are discussed as well as the mechanisms at work. Elevated temperature exposure and page location within a block of the memory are shown to have significant effects on the amount of data corruption observed. The hardness assurance implications of these effects are discussed.

Electron-Induced Single-Event Upsets in 45-nm and 28-nm Bulk CMOS SRAM-Based FPGAs Operating at Nominal Voltage

Electron-induced single-event upsets (SEUs) are observed in 45-nm and 28-nm bulk complementary metal-oxide semiconductor static random-access memory-based field-programmable gate arrays (FPGAs) operating at nominal voltage at a 20-MeV electron LINAC facility. Upsets are recorded in the embedded random-access memory (RAM) and configuration RAM of the FPGAs. This paper is the first to show electron-induced SEUs in a commercial-off-the-shelf device operating at nominal voltage. The measured electron-induced SEU cross sections are between 10 - 18 and 10 - 17 cm2/bit depending on the device and memory cell tested. Monte Carlo simulations show that the upsets are due to rare indirect ionization events.

Interrupted PROGRAM and ERASE Operations for Characterizing Radiation Effects in Commercial NAND Flash Memories

A technique of interrupting PROGRAM and ERASE operations is used to extract information about the analog characteristics of commercial NAND Flash memory cells. The number of interrupted PROGRAM or ERASE operations required to cause a bit to change state is shown to be modified by program/erase stress, total ionizing dose, and heavy ion exposure. These modifications allow for the detection of stresses far below the thresholds for memory cell failure.

Using Charge Accumulation to Improve the Radiation Tolerance of Multi-Gb NAND Flash Memories

Consecutive write operations on 42-nm and 60-nm single-level cell (SLC) Samsung NAND flash memories are shown to significantly improve both the total ionizing dose response and the single event upset tolerance of the memory. By writing these SLC flash memories multiple times, more charge is placed on the floating gate. This accumulated charge leads to a larger amount of radiation needed to corrupt the data. The work presented in this paper illustrates a path forward to the development of a multi-gigabit rad-hard non-volatile memory.

Impact of X-Ray Exposure on a Triple-Level-Cell NAND Flash

The total ionizing dose response of a triple-level-cell (TLC) NAND flash is shown to be low enough that data corruption can occur as a result of an x-ray inspection. Only a few seconds of x-ray exposure corresponding to a total dose of merely 50 rad(Si) in a real-time x-ray source are required to induce errors. An in-depth total dose analysis shows which pages of the memory and data patterns are the most susceptible to radiation. The results show that TLC NAND flash devices are not suitable for use in high radiation environments, and that care must be taken when exposing them to even small x-ray exposures like those present in a circuit board inspection.

Characterizing Radiation and Stress-Induced Degradation in an Embedded Split-Gate NOR Flash Memory

Radiation and stress-induced degradation are characterized in split-gate NOR flash cells through a set of unique experiments. Radiation and program/erase stress on the bit cells is shown to create both positive and negative traps in the oxide around the floating gate cell. The annealing temperature following radiation determines the rate at which oxide traps are neutralized. To analyze both program/erase and radiation induced damage in greater detail; partial program and erase operations are performed. The implications of this work for both radiation hardness assurance testing and device reliability are discussed.

Hardness Assurance for Total Dose and Dose Rate Testing of a State-of-the-Art Off-Shore 32 nm CMOS Processor

Hardness assurance test results of an Advanced Micro Devices, Inc. (AMD) 32 nm processor for total dose and dose rate response are presented. Testing was performed using commercial motherboards and software stress applications versus more traditional automated test equipment (ATE).

Low-Energy Electron Irradiation of NAND Flash Memories

Data on NAND Flash memories exposed to electrons with energies ranging from 20 keV to 100 keV are presented. When the memories are exposed to electrons below 100 keV, the total-dose induced data corruption is significantly greater than when tested to the same total dose in a Co-60 source due to dose enhancement effects. In addition, even in an extremely radiation soft NAND flash, no electron-induced single-event upsets were observed in this work.

Single Event Effects in 14-Nm Intel Microprocessors

Heavy ion and proton test results on multiple commercial 14-nm Intel microprocessors are presented. Testing was performed using commercial motherboards with a mixture of commercial and custom software. Machine check errors, system crashes, graphical glitches, and isolated events with temporary or permanent loss of functionality referred to as hard failures were observed during testing. The hard failures observed while testing the Intel 5th Generation Broadwell 14-nm devices were caused by a companion 32-nm planar bulk CMOS die in the multi-chip package.

Alpha-particle and neutron-induced single-event transient measurements in subthreshold circuits

Experimental data from alpha particle, neutron, and heavy ion testing are discussed and analyzed from a sub-threshold voltage SET characterization circuit. Using a Schmitt trigger inverter target chain fabricated in a 28-nm bulk CMOS process, SET pulse widths are captured from an operating voltage down to 0.32 V. These results show that energetic particles can induce SET pulse widths that range up to hundreds of nanoseconds when operating at voltages well below the nominal voltage. Additionally, the results show that sub-Vt circuits are significantly more susceptible, as compared to circuits operating at nominal voltages, to low-energy particles inducing SETs that have a high probability of being latched as errors in a combinatorial logic design.