Matthew J. Gadlage

Single event transient pulse widths in digital microcircuits

The radiation effects community has long known that single event transients in digital microcircuits will have an increasing importance on error rates as device sizes shrink. However separating these errors from static errors in latch cells has often proved difficult. Thus determining both the significance and the nature of these transient errors has not been easy. In this study, by utilizing a latch that is radiation hard at static clock frequencies the errors due to transients could be separated. By separating the transient error rate from the static upset error rate, the pulse structure of the propagating transients was studied using SPICE. The implications of these pulsewidths will also be discussed.

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

Single event transient pulsewidth measurements using a variable temporal latch technique

A new test structure was designed for measuring the pulsewidths of transients created by SETs. Experimental data was gathered using heavy ions from LETs of 11.5 to 84MeV-cm/sup 2//mg. The pulsewidths of SETs generated using heavy ions are measured using a variable temporal latch. Our SETs widths at low LETs agree exceptionally well with previous localized beam measurements.

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or ¿quench,¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.

Digital Single Event Transient Trends With Technology Node Scaling

We have measured the single-event-transient (SET) width as a function of cross-section over three CMOS bulk/epitaxial technology nodes (0.25, 0.18 and 0.13 mum) using an identically scaled programmable-delay temporal-latch technique. Both the maximum width of the SET pulse and the cross-section are shown to depend primarily on the supply voltage, with a substantial increase in transient width and cross-section with lower operating potentials

The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

Heavy-ion microbeam and broadbeam data are presented for a 65 nm bulk CMOS process showing the existence of pulse quenching at normal and angular incidence for designs where the pMOS transistors are in common n-wells or isolated in separate n-wells. Experimental data and simulations show that pulse quenching is more prevalent in the common n-well design than the separate n-well design, leading to significantly reduced SET pulsewidths and SET cross-section in the common n-well design.

Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes

Single event transient (SET) pulse widths produced from heavy ion irradiation in digital ICs are measured using a variable-delay temporal-latch test structure. We show for the first time that there is a wide distribution of SET pulse widths created by heavy ion radiation in digital CMOS logic at given linear energy transfer (LET) levels. We were able to measure SET pulse widths from as short as 344 ps to greater than 1.5 ns in 0.18 /spl mu/m CMOS technology at LETs greater than 80 MeV-cm /sup 2//mg. Depending on LET, the cross section of the very long SET pulses were as much as four orders of magnitude smaller than for the shorter pulse widths. This has substantial implications for hardening techniques; specifically, we now know that we can dramatically improve the SET hardness without suffering the speed penalties required to remove the longest transients.

Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes

Digital single-event transient (SET) measurements in a bulk 65-nm process are compared to transients measured in 130-nm and 90-nm processes. The measured SET widths are shorter in a 65-nm test circuit than SETs measured in similar 90-nm and 130-nm circuits, but, when the factors affecting the SET width measurements (in particular pulse broadening and the parasitic bipolar effect) are considered, the actual SET width trends are found to be more complex. The differences in the SET widths between test circuits can be attributed in part to differences in n-well contact area. These results help explain some of the inconsistencies in SET measurements presented by various researchers over the past few years.

Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate of SETs longer than 1 ns.

Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS

A novel circuit design for separating single-event transients due to N-hits and P-hits is described. Measurement results obtained from a 65 nm technology using heavy-ions show different dominant mechanisms for charge collection for P-hits and N-hits. The data collected represent the first such separation of SET pulse widths for 65 nm bulk CMOS technology. For low LET particles, N-hit transients are longer, but for high LET particles, P-hit transients are longer. N-well depth and the parasitic bipolar effect are shown to be the most important parameters affecting transient pulse widths.