tthew Ma

Enhancing microprocessor immunity to power supply noise with clock/data compensation

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach.

Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.

Enhanced thermal management for future processors

An enhanced thermal management mechanism that reduces power by scaling frequency and voltage in response to excessive temperatures is presented. The voltage transition process is done transparently to the execution of applications. The enhanced mechanism achieves an /spl sim/50% power reduction while limiting the performance impact to only /spl sim/20% for the duration of the thermal event. The approach allows the processor to meet its performance and reliability goals without additional thermal solution costs.

Development and validation of an electromagnetic distributed power grid model for the 90nm Pentium/spl reg/ 4 processor

In this paper, we show that it is necessary to include the distributed effects of the power grid to accurately model the power supply noise for high frequency microprocessors. We show that high frequency resonances can be entirely missed if such effects are not modeled. Finally we prove the theory with experimental validation on the 90 nm Pentium/spl reg/ 4 microprocessor.

Infrared Ray Emission (IREM) Based Post-Silicon Power Debug Flows Developed for Chip Power Performance

Pre-silicon power modeling, post-silicon power validation, and power debugs design efforts have significantly increased to meet speed performance, reliability deliverables and design robustness for manufacturing. IREM based power debug flow has been developed to isolate marginal circuits with excessive static and dynamic power consumption. Three root cause analysis cases are presented to demonstrate the success of this novel post-silicon debug flow