Tawfik Rahal-Arabi

Enhancing microprocessor immunity to power supply noise with clock/data compensation

This paper demonstrates an alternative to the conventional wisdom that microprocessors require a flat impedance spectrum across a broad range of frequencies in order to deliver maximum operating frequency. Delivering this impedance requires large amounts of on-die capacitance. We show through extensive analysis techniques that proper co-design of the clock and power distribution networks can relax this requirement, saving the area and leakage power needed for on-die decoupling. Measurements made on 130- and 180-nm processors validate the approach.

Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery

In this paper, we present an empirical approach for the validation of the power supply impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.

A JTAG based AC leakage self-test

For the last decade, the manufacturing cost per transistor has been exponentially decreasing. The test cost, however, has been decreasing at a much slower rate and now occupies a significant portion of the total cost of a microprocessor. To address this problem, many companies have planned to gradually move away from functional testing to less expensive structural and system level testing. The fundamental cost difference between these techniques comes from a reduction in the number of pins directly driven by the tester. This work describes a new technique that allows a tester to determine if all of the pins on a chip have acceptable leakage without requiring the tester to actually contact each individual pin.

Design and validation of the core and IOs decoupling of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors

In this paper, we present the design approach and an empirical validation of the power supply decoupling network with particular emphasis on on-die capacitance. The impact of die decoupling on core performance for the 0.18 micron version of the Pentium/spl reg/ 4 has been presented previously (T. Rahal-Arabi et al, VLSI Circ. Symp. Dig. of Tech. Papers, pp. 220-223, 2002). This paper complements the previous work by presenting the design and validation approach for the IO power supply of both the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors. As the Pentium/spl reg/ III processor has separate IO and core supplies, it is a more suitable vehicle for the IO validation. The design approach relies on using the power supply impedance model to determine the required decoupling. The model is widely used in the design of high speed systems (A. Waizman and Chee-Yee Chung, IEEE Conf. Electrical Perf. of Electron. Packaging, pp. 65-68, 2000) but this paper shows that it is less adequate to evaluate performance. The validation approach consists of building several silicon wafers of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors with various amounts of decoupling. Extensive measurements are then conducted at the silicon, package, and system levels.

Optimization and sensitivity analysis of multiconductor transmission line networks

This paper describes a numerical approach and a design methodology of using a frequency domain technique for the optimization and sensitivity analysis of high speed multiconductor transmission line systems. To demonstrate the usefulness of this technique, the numerical frequency domain results have been validated by time domain simulations. The technique has also been used to demonstrate the superiority of closed loop topologies in terms of their electrical performance. Such topologies were thought to be troublesome and were generally avoided in most of the electronics industry. >

I/O self-leakage test

This work presents the implementation of the self-leakage test, a new approach for unconnected I/O leakage testing. It provides a path for leakage current through the on-chip leakers and uses the voltage drop at the pad to detect a pass/fail condition. A detailed methodology for defining the self-leakage test specifications has been developed. Preliminary silicon data shows that self-leakage test methodology provide a viable method for high-volume monitoring of I/O leakage at minimal on-die DFT (design-for-test) overhead.

A frequency-domain technique for the optimization of the electrical performance of high-speed multiconductor transmission-line networks in VLSI regimes

An efficient technique for the optimization of the electrical performance of multiconductor transmission line and interconnect networks in VLSI regimes that is based on the minimization of an error function is described. The technique is particularly useful in the design of printed-circuit-board (PCB) interconnects as it significantly reduces the number of time- and/or frequency-domain simulations required to ensure the functionality of a system design. To demonstrate the usefulness of the technique, several numerical examples have been solved and validated by time- and frequency-domain simulations. >

Development and validation of an electromagnetic distributed power grid model for the 90nm Pentium/spl reg/ 4 processor

In this paper, we show that it is necessary to include the distributed effects of the power grid to accurately model the power supply noise for high frequency microprocessors. We show that high frequency resonances can be entirely missed if such effects are not modeled. Finally we prove the theory with experimental validation on the 90 nm Pentium/spl reg/ 4 microprocessor.

Designing for Low Power

In the last few years, power and power delivery have become the major concerns to computing platforms. The emphasis on power led to several fundamental changes in the design approach of high performance microprocessors. The most notable and visible change was the move to more energy efficient architectures such as the multi-cores. Less visible but equally important changes were also achieved at the design and packaging levels. In this paper, we present some of these fundamental changes. We show how they were applied and validated on a lead 65nm microprocessor leading to significant power savings

Platform modeling for power forecasting and optimization

This paper presents platform power modeling and its usage for power forecasting and optimization of state-of-art mobile platforms that use multi-core microprocessors with other integrated silicon components. The developed methodologies improve prediction accuracy and reduce run time compared to traditional methods of analyzing individual components each on their own then adding them together.