Matthew R. Guthaus

Non-uniform clock mesh optimization with linear programming buffer insertion

Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.

Distributed LC resonant clock tree synthesis

Clock networks in high-performance designs are extremely power hungry. One potential method for reducing the power consumption is to use distributed LC tanks in which energy is conserved by shifting it between electrical and magnetic forms at the resonant frequency. However, no physical algorithms to physically synthesize resonant trees have been proposed. In order to utilize such techniques in ASICs, this work presents the first algorithm to synthesize resonant regional clock trees. Our results suggest that, on average, we can reduce clock power consumption by 41.7% at 2Ghz with no degredation to skew compared to a minimum buffer insertion algorithm.

Distributed LC Resonant Clock Grid Synthesis

Clock distribution networks can consume 35-70% of total chip power in high-performance designs. Resonant clocks can potentially reduce this power by recycling the energy using on-chip inductors. We propose the first automated algorithm called Resonant clOCK Synthesis (ROCKS) that includes distributed LC tank placement, a novel AC-based resonant grid buffer sizing, and resonant grid buffer incremental placement optimization. Experimental results show that using inductors limited to 30% of one metal layer, the resonant clock power can be reduced at least by 40% and the clock buffer area is reduced by at least 53% on average. With larger inductors, it is feasible to achieve up to 90% power savings.

Revisiting automated physical synthesis of high-performance clock networks

High-performance clock distribution has been a challenge for nearly three decades. During this time, clock synthesis tools and algorithms have strove to address a myriad of important issues helping designers to create faster, more reliable, and more power efficient chips. This work provides a complete discussion of the high-performance ASIC clock distribution using information gathered from both leading industrial clock designers and previous research publications. While many techniques are only briefly explained, the references summarize the most influential papers on a variety of topics for more in-depth investigation. This article also provides a thorough discussion of current issues in clock synthesis and concludes with insight into future research and design challenges for the community at large.

Distributed Resonant clOCK grid Synthesis (ROCKS)

Clock distribution networks can consume 35–70% of total chip power in high-performance designs [13]. Resonant clocks can potentially reduce this power by recycling the energy using on-chip inductors. We propose the first automated Resonant clOCK Synthesis (ROCKS) algorithm. Experimental results show that with 10% inductor area, clock power can be reduced by 34%. With more inductor area, up to 90% power savings is shown feasible.

High-performance clock mesh optimization

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

Package-chip co-design to increase flip-chip C4 reliability

The magnitude of the I/O requirements for modern ICs continues to increase due to the growing complexity and size of ICs. The large I/O count found on most ICs have forced most designers to use flip-chip packaging instead of wire bonded packaging. Unfortunately, the solder bumps in flip-chip packages are susceptible to failure, especially in the presence of high temperatures which can cause large stresses and strains leading to mechanical failure of the bump. In this paper, we present a simplified stress/strain/fatigue model that can be used during floorplanning to optimize for package reliability. We also demonstrate a quadratic C4 bump placement method that can be used during floorplanning to increase C4 bump reliability. Our experimental results show that this co-optimization can increase the lifetime of C4 bumps by about 47× with only a modest 3% increase in HPWL wirelength.

Library-aware resonant clock synthesis (LARCS)

Clock grids are often used in high-performance ASIC designs because of their low skew and robustness to variations. Resonant clock grids have the potential to reduce the power consumption of these high-performance clocks without sacrificing the skew and robustness of a clock grid. We present the first methodology to synthesize high-performance distributed resonant LC tank clock grids that utilize a pre-characterized inductor library. The use of a library reduces designer effort and total inductor area when compared with previous resonant clock grids while still attaining 59% power reduction and competitive skew when compared to traditional buffered clock grids.

Clock tree synthesis with data-path sensitivity matching

This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization disregard clock tree variation, we consider both. Using both clock and data-path variations together, we present a novel sensitivity-matching algorithm that allows clock tree skews to be intentionally correlated with data-path sensitivities to ameliorate timing violations due to variation. Our statistical tuning shows an improvement in terms of expected clock skew and clock skew variation over previously published robust algorithms.

CURRENT-MODE CLOCK DISTRIBUTION

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop (CMPFF) using a representative 45 nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.