Riadul Islam

TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

This paper presents a true single-phase clock (TSPC) flip-flop that is robust against radiation-induced single event upsets (SEUs) or soft errors. The flip-flop consists of an input stage that uses a single phase clock to pass the data to a storage unit at the positive edge of the clock. The single phase clock enables designing power-efficient and easily-routed clock-tree and reducing the NBTI effect on the setup and hold times. The storage unit consists of the SEU robust dual interlocked cell (DICE), which has four nodes that replicate the data bit and its complement for recovering from a single event transient (SET). Two nodes with the same logic value inside the storage unit drive a C-element at the output. The C-element masks the propagation of any SET from the internal nodes of the storage unit to the output. The proposed flip-flop consists of only 22 transistors, consumes smaller area, and exhibits as much as 12% lower power-delay product when compared with a recently reported SEU robust flip-flop implemented in a commercial 65nm CMOS technology.

CURRENT-MODE CLOCK DISTRIBUTION

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop (CMPFF) using a representative 45 nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.

Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

In this paper, we present a novel single event upset (SEU) hardened latch. The latch consists of a new 12 transistor (12T) SEU hardened storage cell and a C-element. It is insensitive to single event transient (SET) affecting its internal and output nodes. The differential writing capability of the proposed storage cell is very attractive for designing flip-flops. In addition, we present a high performance SEU hardened D type edge triggered flip-flop, particularly attractive for low data switching activity. The flip-flop utilizes an output feedback connection to the input register stage, in order to reduce power consumption at low data switching activity and eliminate the hold time constraint from traditional clocked CMOS register. We have implemented the proposed latch and the flip-flop in a standard 65 nm CMOS technology. We have investigated power consumptions, propagation delay, SET sensitivity and the area penalty of the proposed latch and flip-flop comparing with the recently reported SEU hardened latches and flip-flops. The proposed latch exhibits as much as 17% lower power-delay product (PDP) compared to recently reported SEU hardened latch, and the proposed flip-flop exhibits lower or comparable PDP compared to recently reported SEU hardened flip-flop while offering more robustness to particle induced SET.

Differential current-mode clock distribution

In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential current-mode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.

A high performance clock precharge SEU hardened flip-flop

Saving power consumption is the most important aspect of nanoscale ASIC and system-on-chips (SOCs). At the same time, due to the low supply voltage and reduced node capacitance, nanoscale integrated circuits are highly susceptible to energetic particle-induced transient data upsets (SEUs). In this paper, we propose a high-speed SEU hardened flip-flop. The flip-flop consists of a unique soft error robust storage (SERS) latch, a novel input transfer unit, and a unique two-input output buffer. With the rising edge of the clock, the transfer unit provides a narrow time window that passes the data to the SERS latch. The latch stores the data values at two storage nodes and two redundant nodes. The two-input output buffer, which is driven by the two storage node of the same logic, masks the propagation of any transient to the output. Post-layout simulations in 65nm CMOS technology show that the flip-flop exhibits as much as 52% lower power-delay product and 25% less area compared to recently reported soft error robust flip-flops.

LC resonant clock resource minimization using compensation capacitance

Distributed-LC resonant clock distribution is a viable technique to reduce clock distribution network (CDN) dynamic power. However, resonant clocks can require significant on-chip resources to form the inductors and decoupling capacitors which discourages adoption. This paper uses a compensation capacitor (Cc) to reduce the overhead of the on-chip inductor and capacitor resources without changing the performance of a distributed-LC resonant clock. Analysis on the ISPD clock benchmarks show nearly 12% reduction in passive device area compared to previous resonant clocks while still saving 49.9% power over traditional buffered clocks.

Switched capacitor quasi-adiabatic clocks

Clock Distribution Networks (CDNs) in high speed designs can consume 30-50% of the total chip dynamic power. Adiabatic clock circuits can save some of this power, but these depend on a time varying power supply which is difficult to implement in practice. In this paper, we present the first quasi-adiabatic clock circuit with a constant supply voltage at high speeds. Our proposed adiabatic clocks attain an average 23% clock power savings with better slew rate and the same skew compared to traditional buffered clocks.