Matthias Ivers

Providing accurate event models for the analysis of heterogeneous multiprocessor systems

This paper proposes a new method for deriving quantitative event information for compositional multiprocessor performance analysis. This procedure brakes down the complexity into the analysis of individual components (tasks mapped to resources) and the propagation of the timing information with the help of event models. This paper improves previous methods to derive event models in a multiprocessor system by providing tighter bounds and allowing arbitrarily shaped event models. The procedure is based on a a simple yet expressive resource model called the multiple event busy time which can be derived on the basis of classical scheduling theory -- it can therefore be provided for a large domain of scheduling policies. Our experiments show that overestimation by previous methods can be reduced significantly.

Integrated analysis of communicating tasks in MPSoCs

Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication networks, basic operations of every embedded application pose a challenge for precise system analysis. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures either focus on system level and allow only limited task models, or focus on activities inside a component, abstracting system level influences by over estimations. In this paper, we identify feedbacks of the system behavior that directly or indirectly impact local execution. To tackle these complex interactions we present a novel technique to integrate an extended component level scheduling analysis with refined system level approaches. Bringing the different levels of abstraction together allows the analysis of a new class of interacting applications and architectures - which could not be addressed on a single level alone. On the component level, we investigate two scheduling behaviors more closely, namely stalling during external requests, and allowing context-switches to other tasks that are ready. For both, we present a precise response time analysis. Finally, we compare the scheduling techniques with respect to real-time requirements.

Memory Access Patterns for the Analysis of MPSoCs

Unlike distributed systems, multiprocessor systems-on-chip often cannot integrate all memory needed for high performance applications within each processor. Hence, accesses to instruction and data memory use the same communication infrastructure as communication between processes. In this paper, we give an overview on an approach to analyze system timing in the presence of memory and coprocessor accesses in MpSoC systems and present a method to derive safe bounds on the traffic generated by tasks as well as resources with multiple tasks mapped to it

Probabilistic Network Loads with Dependencies and the Effect on Queue Sojourn Times

For the dimensioning of shared resources, the latency and utilization of the service is a vital design characteristic. The throughput and latency is as important for e.g. network streaming applications as in e.g. (small-scale) distributed embedded systems interacting with physical processes.

A Polynomial-Time Algorithm for Computing Response Time Bounds in Static Priority Scheduling Employing Multi-linear Workload Bounds

Despite accuracy, analysis speed is sometimes a concern for the performance analysis of real-time systems, e.g. if to performed at runtime for online admission tests. As of today, several algorithms to compute an upper bound to the worst-case response time of a task scheduled under static priority preemptive scheduling with polynomial run-time have been proposed. Most approaches assume periodic activation of all tasks, some allow activation jitter. We generalize the approach to support convex activation patterns, by using multi-linear workload approximations and introduce the possibility to model processor availability to the task set under analysis.

Dependency-aware stochastic analysis of chained execution times

For the design of complex embedded systems, early performance estimation based on models of subsystems is used to decide about key parameters. With stochatic component models coming from different suppliers, the system integrator has the responsiblity to derive a meaningful system performance characterization from different component models.