Mattias Borg

Controlling the Abruptness of Axial Heterojunctions in III-V Nanowires: Beyond the Reservoir Effect

Heterostructure nanowires have many potential applications due to the avoidance of interface defects by lateral strain relaxation. However, most heterostructure semiconductor nanowires suffer from persistent interface compositional grading, normally attributed to the dissolution of growth species in the common alloy seed particles. Although progress has been made for some material systems, most binary material combinations remain problematic due to the interaction of growth species in the alloy. In this work we investigate the formation of interfaces in InAs-GaAs heterostructures experimentally and theoretically and demonstrate a technique to attain substantially sharper interfaces. We show that by pulsing the Ga source during heterojunction formation, In is pushed out before GaAs growth initiates, greatly reducing In carry-over. This procedure will be directly applicable to any nanowire system with finite nonideal solubility of growth species in the alloy seed particle and greatly improve the applicability of these structures in future devices.

High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires

We present electrical characterization of broken gap GaSb-InAsSb nanowire heterojunctions. Esaki diode characteristics with maximum reverse current of 1750 kA/cm(2) at 0.50 V, maximum peak current of 67 kA/cm(2) at 0.11 V, and peak-to-valley ratio (PVR) of 2.1 are obtained at room temperature. The reverse current density is comparable to that of state-of-the-art tunnel diodes based on heavily doped p-n junctions. However, the GaSb-InAsSb diodes investigated in this work do not rely on heavy doping, which permits studies of transport mechanisms in simple transistor structures processed with high-κ gate dielectrics and top-gates. Such processing results in devices with improved PVR (3.5) and stability of the electrical properties.

Vertical III-V nanowire device integration on Si(100).

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneou...

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

This paper presents dc and RF characterization as well as modeling of vertical InAs nanowire (NW) MOSFETs with L_G=200 nm and Al₂O₃/HfO₂ high-κ dielectric. Measurements at V_DS=0.5 V show that high transconductance (g_m=1.37 mS/μm), high drive current (I_DS=1.34 mA/μm), and low ON-resistance (R_ON=287 Ωμm) can be realized using vertical InAs NWs on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, S_VG·L_G·W_G, is determined to be lowered by one order of magnitude compared with similar devices with a high-κ film consisting of HfO₂ only. In addition, with a virtual source model we are able to determine the intrinsic transport properties. These devices (L_G=200 nm) show a high injection velocity (v_inj=1.7×10⁷ cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.

Diameter Limitation in Growth of III-Sb-Containing Nanowire Heterostructures.

The nanowire geometry offers significant advantages for exploiting the potential of III-Sb materials. Strain due to lattice mismatch is efficiently accommodated, and carrier confinement effects can be utilized in tunneling and quantum devices for which the III-Sb materials are of particular interest. It has however proven difficult to grow thin (below a few tens of nanometers), epitaxial III-Sb nanowires, as commonly no growth is observed below some critical diameter. Here we explore the processes limiting the diameter of III-Sb nanowires in a model system, in order to develop procedures to control this effect. The InAs-GaSb heterostructure system was chosen due to its great potential for tunneling devices in future low-power electronics. We find that with increasing growth temperature or precursor partial pressures, the critical diameter for GaSb growth on InAs decreases. To explain this trend we propose a model where the Gibbs-Thomson effect limits the Sb supersaturation in the catalyst particle. This understanding enabled us to further reduce the nanowire diameter down to 32 nm for GaSb grown on 21 nm InAs stems. Finally, we show that growth conditions must be carefully optimized for these small diameters, since radial growth increases for increased precursor partial pressures beyond the critical values required for nucleation.

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a sub-thermal SS would only be achievable for Dit <; 5 x 1011 cm-2eV-1 at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of Dit <; 1 x 1012 cm-2eV-1 for vertical InAs/Si NW TFETs with larger diameters.

Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si

A comprehensive investigation of InAs epitaxy on silicon using template-assisted selective epitaxy is presented. The variation in axial growth rate of InAs nanowires inside oxide nanotube templates is studied as function of nanotube diameter (20–140 nm), growth time (0–30 min), growth temperature (520–580 °C), V/III ratio (40–160), nanotube spacing (300–2000 nm), and substrate crystal orientation. It is found that the effective V/III ratio is reduced at least by a factor of two within the nanotube templates compared to the outside, detectable by changes in the growth facet morphology. The reduced V/III ratio originates from the different transport mechanisms for the As and In precursor species; As and In species are both transported by Knudsen diffusion in the vapor, but an additional contribution of In surface diffusion reduces the V/III ratio. The results reveal the interplay of growth parameters, crystal facets and template geometry and thus are generally applicable for nanoscale selective epitaxy.

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a room-temperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET Ion performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects

Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.