Davide Cutaia

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneou...

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a sub-thermal SS would only be achievable for Dit <; 5 x 1011 cm-2eV-1 at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of Dit <; 1 x 1012 cm-2eV-1 for vertical InAs/Si NW TFETs with larger diameters.

Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si

A comprehensive investigation of InAs epitaxy on silicon using template-assisted selective epitaxy is presented. The variation in axial growth rate of InAs nanowires inside oxide nanotube templates is studied as function of nanotube diameter (20–140 nm), growth time (0–30 min), growth temperature (520–580 °C), V/III ratio (40–160), nanotube spacing (300–2000 nm), and substrate crystal orientation. It is found that the effective V/III ratio is reduced at least by a factor of two within the nanotube templates compared to the outside, detectable by changes in the growth facet morphology. The reduced V/III ratio originates from the different transport mechanisms for the As and In precursor species; As and In species are both transported by Knudsen diffusion in the vapor, but an additional contribution of In surface diffusion reduces the V/III ratio. The results reveal the interplay of growth parameters, crystal facets and template geometry and thus are generally applicable for nanoscale selective epitaxy.

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a room-temperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET Ion performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with ION of a few μA/μm for |VDS| = |VGS| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS.

High-Mobility GaSb Nanostructures Cointegrated with InAs on Si

GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.

Complementary III–V heterojunction lateral NW Tunnel FET technology on Si

We demonstrate for the first time a technology which allows the monolithic integration of both p-type (InAs-Si) and n-type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ~70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS = -0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).

Monolithic integration of multiple III-V semiconductors on Si for MOSFETs and TFETs

In this paper we report on our work on the monolithic integration of various III-V compounds on Si using template-assisted selective epitaxy (TASE) and its application for electronic devices. Nanowires, crossbar nanostructures, and micron-sized sheets are epitaxially grown on Si via metal-organic chemical vapor deposition and form the basis for III-V MOSFETs and Tunnel FETs. Epitaxy conditions specific to TASE are discussed and material quality assessed. Here, we focus on InAs and GaSb as a potential all-III-V alternative to complementary group IV technology. Scaled n-FETs as well as both n- and p-channel TFETs are fabricated on Si and illustrate the potential of TASE.

Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kanes tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.

Complementary III–V heterostructure tunnel FETs

In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with Ion of a couple of μA/μm (|VGS| = |VDS| = 0.5V) combined with average subthreshold swing, SS, of 70-80mV/dec. The all III-V n-TFETs show about an order of magnitude higher Ion, but their SS is limited by the non-optimized gate stack and doping profiles. Thorough simulation studies of our devices show trap-assisted tunneling at the heterojunction to be the main limitation on SS. We will discuss the impact of different trap mechanisms and compare our results with other experimental data.