Heinz Schmid

Nanoparticle printing with single-particle resolution

Bulk syntheses of colloids efficiently produce nanoparticles with unique and useful properties. Their integration onto surfaces is a prerequisite for exploiting these properties in practice. Ideally, the integration would be compatible with a variety of surfaces and particles, while also enabling the fabrication of large areas and arbitrarily high-accuracy patterns. Whereas printing routinely meets these demands at larger length scales, we have developed a novel printing process that enables positioning of sub-100-nm particles individually with high placement accuracy. A colloidal suspension is inked directly onto printing plates, whose wetting properties and geometry ensure that the nanoparticles only fill predefined topographical features. The dry particle assembly is subsequently printed from the plate onto plain substrates through tailored adhesion. We demonstrate that the process can create a variety of particle arrangements including lines, arrays and bitmaps, while preserving the catalytic and optical activity of the individual nanoparticles.

Toward Nanowire Electronics

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

Capillary pumps for autonomous capillary systems

Autonomous capillary systems (CSs), where liquids are displaced by means of capillarity, are efficient, fast and convenient platforms for many bioanalytical applications. The proper functioning of these microfluidic devices requires displacing accurate volumes of liquids with precise flow rates. In this work, we show how to design capillary pumps for controlling the flow properties of CSs. The capillary pumps comprise microstructures of various shapes with dimensions from 15-250 microm, which are positioned in the capillary pumps to encode a desired capillary pressure. The capillary pumps are designed to have a small flow resistance and are preceded by a constricted microchannel, which acts as a flow resistance. Therefore, both the capillary pump and the flow resistance define the flow rate in the CS, and flow rates from 0.2-3.7 nL s(-1) were achieved. The placement and the shape of the microstructures in the capillary pumps are used to tailor the filling front of liquids in the capillary pumps to obtain a reliable filling behaviour and to minimize the risk of entrapping air. The filling front can, for example, be oriented vertically or tilted to the main axis of the capillary pump. We also show how capillary pumps having different hydrodynamic properties can be connected to program a sequence of slow and fast flow rates in a CS.

Donor deactivation in silicon nanostructures

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

Hysteresis in lithographic arrays of permalloy particles: Experiment and theory (invited)

We have investigated the effects of particle size and aspect ratio on the hysteresis in controlled arrays of small magnetic particles. The arrays of permalloy particles were fabricated via electron‐beam lithography. Each array consists of ∼ 106 identical, uniformly spaced particles. Hysteresis loops measured with an alternating‐gradient magnetometer for particles ∼5–0.1 μm are presented. We find an increase in the coercive force as the particle width decreases below 0.3 μm due to a change in the switching mechanism from domain‐wall nucleation and wall motion to vortex nucleation and vortex motion. A novel angular dependence of the loops is described in detail. Results from ab initio micromagnetic calculations on isolated rectangular Permalloy particles are compared, where applicable, with the measurements. We find excellent qualitative and, in selected cases, quantitative agreement between the experiments and calculations.

Silicon nanowire tunneling field-effect transistors

We demonstrate the implementation of tunneling field-effect transistors (TFETs) based on silicon nanowires (NWs) that were grown using the vapor-liquid-solid growth method. The Si NWs contain p-i-n+ segments that were achieved by in situ doping using phosphine and diborane as the n- and p-type dopant source, respectively. Electrical measurements of the TFETs show a band-to-band tunneling branch in the transfer characteristics. Furthermore, an increase in the on-state current and a decrease in the inverse subthreshold slope upon reducing the gate oxide thickness are measured. This matches theoretical calculations using a Wenzel Kramer Brillouin approximation with nanowire diameter and oxide thickness as input parameters.

LIGHT-COUPLING MASKS FOR LENSLESS, SUB-WAVELENGTH OPTICAL LITHOGRAPHY

Light-coupling masks (LCMs) based on structured organic polymers that make conformal contact with a substrate can constitute an amplitude mask for light-based lithographies. The LCM is exposed through its backside, from where the light is differentially guided by the structures towards the substrate. Images of arbitrarily shaped features having dimensions much smaller than that of the vacuum wavelength of the exposing light are formed in the resist in a 1:1 correspondence to their size in light-guiding portions of the mask. LCMs allow pattern replication at high resolution and densities over large areas in photoresist without the need for elaborate projection optics.

Theory of the point source electron microscope

Abstract The theory of the point source electron microscope including multiple scattering events is formulated. Images are calculated and analyzed for carbon clusters, varbon fibers and large metal films. A Fourier-like transform is then shown to be appropriate for the reconstruction of the object with atomic resolution. Effects due to higher partial waves, multiple scattering and finite image size are examined in detail.

Vertical surround-gated silicon nanowire impact ionization field-effect transistors

One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor technology is the room-temperature (RT) limit of ∼60mV/decade in the inverse subthreshold slope. Here, the authors demonstrate vertical integration of a single surround-gated silicon nanowire field-effect transistor with an inverse subthreshold slope as low as 6mV/decade at RT that spans four orders of magnitude in current. Operation of the device is based on avalanche breakdown in a partially gated vertical nanowire, epitaxially grown using the vapor-liquid-solid method. Low-power logic based on impact ionization field-effect transistors in combination with a vertical architecture is very promising for future high-performance ultrahigh-density circuits.

Si–InAs heterojunction Esaki tunnel diodes with high current densities

Si–InAs heterojunction p-n diodes were fabricated by growing InAs nanowires in oxide mask openings on silicon substrates. At substrate doping concentrations of 1×1016 and 1×1019 cm−3, conventional diode characteristics were obtained, from which a valence band offset between Si and InAs of 130 meV was extracted. For a substrate doping of 4×1019 cm−3, heterojunction tunnel diode characteristics were obtained showing current densities in the range of 50 kA/cm2 at 0.5 V reverse bias. In addition, in situ doping of the InAs wires was performed using disilane to further boost the tunnel currents up to 100 kA/cm2 at 0.5 V reverse bias for the highest doping ratios.