Frederik Leys

Germanium: The Past and Possibly a Future Material for Microelectronics

In 1947, the first transistors were fabricated in Bell Labs using bulk germanium as the semiconducting material. For this work its inventors, John Bardeen and Walter Brattain shared the 1956 Nobel Prize in Physics, along with William Shockley. About a dozen years later, the integrated circuit was independently invented by Jack Kilby, who used Ge substrates, and by Robert Noyce, who used silicon, and for which Kilby received the 2000 Nobel Prize in Physics (Noyce had passed on in 1990). Germanium was the predominant material for solid state devices through the 1950s and early 1960s, but its use was largely replaced with silicon during the 1960s. There are a number of reasons for this shift, but the ready formation of a high quality thermal oxide (SiO2) for silicon as compared to the water soluble oxides for Ge (GeO, GeO2) and the difficulty this poses for device performance and integration is a major reason.

Vapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 10 20 cm -3 at the heterointerface in the Sicap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

In Situ Phosphorus Doping of Germanium by APCVD

Germanium is increasingly being studied for application in advanced nanoelectronic devices, due to its high intrinsic carrier mobility. While broad knowledge and understanding of in-situ doping of Si is available, very little is known on in-situ doping of Ge. Phosphorus has been identified as one of the most promising n-type dopants for Ge, because of its high electrical activity. However, studies of the quality of ion-implanted P-doped Ge layers showed unsatisfactory behavior. A considerable difference between the levels of the electrical solubility and equilibrium solid solubility of P in Ge has been reported. The highest electrically active level of ionimplanted P in Ge reported to date is of 5-6×10 cm. The interest in in-situ doping of Ge was triggered by the possibility of increasing the electrically active levels obtained for n-type dopants at the same time as having better control over the shape of the dopant profile and its location. We present the first results on in-situ P doping of Ge by APCVD.

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

This paper demonstrates for the first time the integration of an HfO2/TiN/poly gate stack and a recessed SiGe S/D module. It also shows that by combining the SiGe stressor with a compressive nitride contact etch stop layer, it is possible to reach improvements in IDSAT of up to 65%, showing that the various strain mechanisms are additive on advanced gate stacks. This way an IDSAT of 422 muA/mum at 20pA/mum I OFF and VDD = 1.1 V can be obtained when a 25% SiGe S/D module is combined with a 1.5 GPa compressive sCESL layer

Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination

Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Selective Epitaxy of Si/SiGe to improve pMOS devices by recessed Source/Drain and/or Buried SiGe Channels

SiGe R. Loo, P. Verheyen, R. Rooyackers, C. Walczyk*, F.E. Leys, D. Shamiryan, P.P. Absil, T. Delande, A. Moussa, J.W. Weijtmans, R. Wise, V. Machkaoutsan, C. Arena, J. McCormack, S. Passefort, H. Sorada, A. Inoue, B.C. Lee, S. Hyun, S. Jakschik, and M. Caymax 1 IMEC, Kapeldreef 75, 3001 Leuven (Belgium), *also Universitat Siegen, Holderlinstrasse 35, 7068 Siegen (Germany), Texas Instruments Inc., 13560 North Central Expressway, Dallas (USA), ASM-Belgium, Kapeldreef 75, 3001 Leuven (Belgium), ASM-America, 3440 East University Drive, Phoenix, (USA), KLA-Tencor Corp. 160 Rio Robles, San Jose (USA), Matsushita assignee at IMEC, Samsung assignee at IMEC, Infineon assignee at IMEC

Parasitic source/drain resistance reduction in n-channel SOI MuGFETs with 15nm wide fins

We report on a set of process improvements leading to parasitic S/D resistance reduction in n-channel MuGFETs with 60 nm tall and 15 nm wide fins. We experimentally determine the contributions to the parasitic S/D resistance arising from the specific regions of the S/D geometry. A 50% reduction in the S/D resistance (from 1235 to 600 /spl Omega/-/spl mu/m) is achieved by introducing various scaled processes, including EOT reduction, elevated S/D, undoped fins and removal of halos, reduction in S/D spacer width, and smaller gate lengths. The combination of these process enhancements leads to a 2/spl times/ increase in I/sub DSAT/, measured at constant I/sub OFF/ (=1nA//spl mu/m) and V/sub DD/=1.3V.

Germanium Deep-Submicron p -FET and n -FET Devices, Fabricated on Germanium-On-Insulator Substrates

A key challenge in the engineering of Ge MOSFETs is to develop a proper Ge surface passivation technique prior to high-κ dielectric deposition to obtain low interface state density and high carrier mobility. A review on some possible treatments to passivate the Ge surface is discussed. Another important aspect is the activation of p- and n-type dopants to form the active areas in devices. Finally, Ge deep submicron n- and p-FET devices fabricated with this technique on germanium-on-insulator substrates, yield promising device characteristics, showing the feasibility of these substrates.

Application of Single-Wafer Wet Cleaning Prior to Epitaxial SiGe Process

Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

Challenges of Single-Wafer Wet Cleaning for Low Temperature Pre-Epitaxial Treatment of SiGe

Epitaxial deposition of strained Si and SiGe to improve electron and hole mobility and Vt shift is becoming more and more part of the standard CMOS processing [1,2]. One of the most important restrictions imposed on advanced CMOS processing is that on thermal budget. For epitaxial growth processes this thermal budget is quite high. The main contribution comes however not from the growth itself, but from the in-situ H2 bake necessary to remove any oxide traces left prior to epi. Without any pre-epi etch, removal of the native oxide requires at least a bake for several minutes at 900 ̊C or higher. When combined with a wet clean which removes the native oxide and passivates the surface (usually H or Cl), this temperature can be reduced to the range of 850-750 ̊C, although this is always at the cost of a remaining C and O peak at the epi-substrate interface.