Maud Baylac

Evidence of the Robustness of a COTS Soft-Error Free SRAM to Neutron Radiation

Radiation tests with 15-MeV neutrons were performed in a COTS SRAM including a new memory cell design combining SRAM cells and DRAM capacitors to determine if, as claimed, it is soft-error free and to estimate upper bounds for the cross-section. These tests led to cross-section values two orders of magnitude below those of typical CMOS SRAMs in the same technology node. MUSCA SEP3 simulations complement these results predicting that only high-energy neutrons ( > 30 MeV) can provoke bit flips in the studied SRAMs. MUSCA SEP3 is also used to investigate the sensitivity of the studied SRAM to radioactive contamination and to compare it with the one of standard CMOS SRAMs. Results are useful to make predictions about the operation of this memory in environments such as avionics.

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45 nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processing mode used.

Evaluation of the sensitivity of a COTS 90-nm SRAM memory at low bias voltage

This paper presents an experimental study of the sensitivity to 14-MeV neutrons to low bias voltage of a COTS 90-nm Cypress SRAM. Experiments involving power supplies ranging from 0.5V to 3.3V are presented and discussed. These results have also been compared with cross-section and SER theoretical predictions.

Some properties of only-SBUs scenarios in SRAMs applied to the detection of MCUs

Statistical properties of experiments in SRAMs with only SBUs are mathematically evaluated. Strategies using deviations of actual data from theory are proposed to extract MCUs from the bulk of errors regardless the SRAM internal structure.

Neutron-Induced Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage

This paper presents an experimental study of the sensitivity to 15-MeV neutrons at low bias voltage of advanced low-power SRAMs by Renesas Electronics. The most interesting results are the occurrence of clusters of bitflips, hard errors only visible at low voltage, appearing along with single event upsets. The physical mechanisms are briefly discussed.

Statistical Deviations From the Theoretical Only-SBU Model to Estimate MCU Rates in SRAMs

This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bit flip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper proposes to evaluate the statistical properties of the sets of corrupted addresses and to compare the results with a mathematical prediction model where all of the events are single bit upsets. A set of rules easy to implement in common programming languages can be iteratively applied if anomalies are observed, thus yielding a classification of errors quite closer to reality (more than 80% accuracy in our experiments).

Sensitivity to Neutron Radiation of a 45 nm SOI Multi-Core Processor

The purpose of this paper is to evaluate the SEU sensitivity of a multi-core SoC working in two different multiprocessing modes. Radiation ground tests were performed with 14 MeV neutrons in GENEPI2 facility. The case study was a 45nm SOI multi-core processor having implemented error correcting code (ECC) and parity in their cache memories.