Maurizio Rebaudengo

Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors

This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

Impact of data cache memory on the single event upset-induced error rate of microprocessors

Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper.

Comparing topological, symbolic and GA-based ATPGs: an experimental approach

The goal of this paper is-to compare from an experimental point of view the performance of three ATPG tools for synchronous sequential circuits. The three tools are stare-of-the-art implementations of the topological, symbolic, and GA-based approaches, respectively. The environment set up for obtaining a fair comparison is described: the same hardware platform, circuit and fault list description, and detection mechanism are adopted. The obtained results allow the reader to more deeply understand the characteristics and relative advantages/disadvantages of these methods.

Partial scan flip flop selection for simulation-based sequential ATPGs

The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the scan flip flops, in general each technique is tailored to a particular ATPG algorithm and results effective when coupled with the right ATPG tool. In this paper, we propose an approach suitable for GA-based ATPGs, which is barred on exploiting some information coming from the ATPG itself we compare the results of our method with the ones of the approach based on cutting the topological loops and use a GA-based ATPG to demonstrate its effectiveness in terms of fault coverage and CPU time.

System-level test bench generation in a co-design framework

Co-design tools represent an effective solution for reducing costs and shortening time-to-market, when System-on-Chip design is considered. In a top-down design flow, designers would greatly benefit from the availability of tools able to automatically generate test benches, which can be used during every design step, from the system-level specification to the gate-level description. This would significantly increase the chance of identifying design bugs early in the design flow, thus reducing the costs and increasing the final product quality. The paper proposes an approach for integrating the ability to generate test benches into an existing co-design tool. Suitable metrics are proposed to guide the generation, and preliminary experimental results are reported, assessing the effectiveness of the proposed technique.

Exploiting the background debugging mode in a fault injection system

This note describes a software-implemented Fault Injection system suited to be used with embedded microprocessor-based boards and based on some features available in the most recent microprocessors and microcontrollers. Although these features were originally introduced to easy code development and debugging, they are very well suited for supporting the implementation of efficient and barely intrusive Fault Injection Systems. In particular, our Fault Injection system exploits the Background Debugging Mode (BDM), available in the last microprocessors and microcontrollers produced by Motorola.