Mauro Cesar Zanella

Rapid prototyping of real-time control laws for complex mechatronic systems: a case study

Rapid prototyping of complex systems embedded in even more complex environments raises the need for a layered design approach. Our example is a mechatronic design taken from the automotive industry and illustrates the rapid-prototyping procedure of real-time-critical control laws. The approach is based on an object-oriented structuring allowing not only central control units but also distributed control units as needed by todays designs. The implementation of control laws is a hardware-in-the-loop simulation, refined in steps and reducing the simulation part at every one of these. On the lower level, common platforms, such as FPGAs, microcontrollers or specialized platforms, can be instantiated.

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems

The presented architecture has the peculiar feature of being self-timed and comprising a fully interlocked pipelining structure which aims at controlling the different computational paths of a system design. One example is the automotive industry where performance, space, cost, size, and weight are of vital importance, the main features of this architecture.

Analysis, Architectures and Modelling of Embedded Systems

Modelling.- State Machine Based Method for Consolidating Vehicle Data.- Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation.- Modelling of Device Driver Software by Reflection of the Device Hardware Structure.- An Infrastructure for UML-Based Code Generation Tools.- A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance.- ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs.- Transaction Level Modelling.- Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support.- Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices.- Modeling Cache Effects at the Transaction Level.- Scheduling and Real-Time Systems.- Event Stream Calculus for Schedulability Analysis.- Real-Time Scheduling in Heterogeneous Systems Considering Cache Reload Time Using Genetic Algorithms.- Task-Dependent Processor Shutdown for Hard Real-Time Systems.- Experimental Evaluation of a Hybrid Approach for Deriving Service-Time Bounds of Methods in Real-Time Distributed Computing Objects.- Simulation, Verification and Test.- Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling.- Formal Verification for Embedded Systems Design Based on MDE.- Systematic Model-in-the-Loop Test of Embedded Control Systems.- Platforms and Processors.- Proteus, a Hybrid Virtualization Platform for Embedded Systems.- Constructing a Multi-OS Platform with Minimal Engineering Cost.- A Synchronization Method for Register Traces of Pipelined Processors.- Automotive Systems.- Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study.- Automatic Transformation of System Models in Automotive Electronics.- Towards a Load Balancing Middleware for Automotive Infotainment Systems.- Case Studies.- Towards an Irritable Bowel Syndrome Control System Based on Artificial Neural Networks.- A Hybrid Hardware and Software Component Architecture for Embedded System Design.- Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture.- Wireless Sensor Networks.- The Case for Interpreted Languages in Sensor Networks.- Characterization of Inaccessibility in Wireless Networks: A Case Study on IEEE 802.15.4 Standard.- FemtoNode: Reconfigurable and Customizable Architecture for Wireless Sensor Networks.- Tutorials.- Efficient Modeling of Embedded Systems Using Computer-Aided Recoding.- New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies.

RABBIT - A Modular Rapid Prototyping Platform for Distributed Mechatronic Systems

A basic idea of the mechatronic design is to decompose a mechatronic system into subsystems in order to make the complex structure manageable. This paper introduces a platform, named RABBIT, which helps the designer in the development of mechatronic systems during the simulation and implementation stages. At these stages, software- and hardware-in-the-loop simulation is usually necessary. Our purpose is to develop a modular hardware and software platform for distributed real-time applications. The hardware comprises three main components: IEEE 1394, MPC555 microcontroller, and FPGA. The central aim of this project is high flexibility and extensibility of the platform. Two case-studies are described to exemplify the implementation of such a platform. One is named X-mobile (a novel modular mechatronic vehicle) and the other is the TESLA system (Test Site for Laboratory Automation).

Towards a high-level synthesis of reconfigurable bit-serial architectures

This paper presents high-level synthesis methods for a fully reconfigurable self-timed synchronous bit-serial pipeline architecture. The idea is to distribute the central control unit. Local controls of the operators are realized through a one-shot implementation of the central control engine. Specialized routing components allow the reconfiguration of the implemented circuit with respect to rapid system prototyping. We describe several kinds of high-level synthesis approaches, especially the scheduling, which can be used for this type of architecture. This means we optimize specific characteristics, like loops, junctions and splitters, during the synthesis phase.

Invariants for distributed local control elements of new synchronous bit-serial architecture

The growing need for application class specific but still flexible data processing leads to a demand of new computer architectures. Reorganization and combination of proven design paradigms are promising ways to reach these goals. The fully re-configurable self-timed bit-serial and fully interlocked MACT architecture is one of those new architectures. Although MACT does not rely on a central controller, its local synchronization still demands special care is taken. This fact is especially true if routers are added to the architecture. In this paper we present fundamental invariants for the high level synthesis of MACT as well as an extended explanation of the routing elements. We prove the usefulness of the architecture by an example implementation of two convolution filters within one dataflow graph.

Embedded System Design: Topics, Techniques and Trends

Over recent years, embedded systems have gained an enormous amount of processing power and functionality. Many of the formerly external components can now be integrated into a single System-on-Chip. This tendency has resulted in a dramatic reduction in the size and cost of embedded systems. As a unique technology, the design of embedded systems is an essential element of many innovations. Embedded System Design: Topics, Techniques and Trends presents the technical program of the International Embedded Systems Symposium (IESS) 2007 held in Irvine, California. IESS is a unique forum to present novel ideas, exchange timely research results, and discuss the state of the art and future trends in the field of embedded systems. Contributors and participants from both industry and academia take active part in this symposium. The IESS conference is organized by the Computer Systems Technology committee (TC10) of the International Federation for Information Processing (IFIP). Timley topics, techniques and trends in embedded system design are covered by the chapters in this book, including design methodology, specification and modeling, embedded software and hardware synthesis, networks-on-chip, distributed and networked systems, and system verification and validation. Particular emphaisis is paid to automotive and medical applications. A set of actual case studies and special aspects in embedded system design are included as well.

Control development for mechatronic systems with a fully reconfigurable pipeline architecture

The dynamic reconfiguration of controller implementations demand a specific processing architecture. Configurable elements are for example FPGAs. The price of FPGAs is mainly determined by the pin number. This means that it is costly to realize large control systems with well-known architectures. In the case of reliable systems (e.g. steer-by-wire steering) a low pin count is not only a factor of cost but also a factor for reliability. This paper presents a new synchronous, fully re-configurable self-timed bit-serial and fully interlocked pipeline architecture called MACT. Due to bit-serial processing, bit-serial input and output systems with low pin count are required. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The presented architecture is optimized for use in embedded systems to control mechatronic systems, but can be also employed in other fields of application. So we furthermore present here the pipeline architecture integration into a mechatronic design process.

A new approach of a self-timed bit-serial synchronous pipeline architecture

Power consumption, area minimization as well as signal delay and reconfiguration with respect to rapid system prototyping make increasing demands on chip design. While design space can be reduced by bit-serial operators, long control lines in synchronous bit-serial architecture usually affect the performance of the circuit. This paper presents a new synchronous, fully reconfigurable self-timed bit-serial and fully interlocked pipeline architecture. Through a one-hot implementation of the central control engine, we realize the local control of the operators. Furthermore, we developed a specialized routing component that allows the reconfiguration of the implementation w.r.t. rapid system prototyping. This realization of the developed architectures provides the freedom of a rapid system prototyping of a given problem. To our knowledge, this is the second paper detailing the implementation of a fully interlocked synchronous architecture after the one by Jacobson et al. (2002) and the first which does not rely on gated clocks to realize the local control of the operators. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The architecture is optimized for the use in embedded systems to control mechatronic systems, but can also be employed in other fields of application.

Distributed HIL simulation of mechatronic systems applied to an agricultural machine

This paper presents an approach to a new software platform for distributed hardware-in-the-loop simulation applied to mechatronic systems.