Max C. Lemme

Efficient Inkjet Printing of Graphene

An efficient and mature inkjet printing technology is introduced for mass production of coffee-ring-free patterns of high-quality graphene at high resolution (unmarked scale bars are 100 μm). Typically, several passes of printing and a simple baking allow fabricating a variety of good-performance electronic devices, including transparent conductors, embedded resistors, thin film transistors, and micro-supercapacitors.

Vertical Graphene Base Transistor

We present a novel graphene-based-device concept for a high-frequency operation: a hot-electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows terahertz operation. Based on energy-band considerations, we propose a specific material solution that is compatible with SiGe process lines.

Graphene-enabled wireless communication for massive multicore architectures

Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

Inkjet Printing of 2D Layered Materials

Inkjet printing of 2D layered materials, such as graphene and MoS2, has attracted great interests for emerging electronics. However, incompatible rheology, low concentration, severe aggregation and toxicity of solvents constitute critical challenges which hamper the manufacturing efficiency and product quality. Here, we introduce a simple and general technology concept (distillation-assisted solvent exchange) to efficiently overcome these challenges. By implementing the concept, we have demonstrated excellent jetting performance, ideal printing patterns and a variety of promising applications for inkjet printing of 2D layered materials.

A simple route towards high-concentration surfactant-free graphene dispersions

A simple solvent exchange method is introduced to prepare high-concentration and surfactant-free graphene liquid dispersion. Natural graphite flakes are first exfoliated into graphene in dimethylformamide (DMF). DMF is then exchanged by terpineol through distillation, relying on their large difference in boiling points. Graphene can then be concentrated thanks to the volume difference between DMF and terpineol. The concentrated graphene dispersions are used to fabricate transparent conductive thin films, which possess comparable properties to those prepared by more complex methods.

A manufacturable process integration approach for graphene devices

Abstract In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2xa0nm) high-quality thermally grown SiO 2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al 2 O 3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000.

RF Performance Projections of Graphene FETs vs. Silicon MOSFETs

A graphene field-effect-transistor (GFET) model calibrated with extracted device parameters and a commercial 65 nm silicon MOSFET model are compared with respect to their radio frequency behavior. ...

Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors

With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.

Strain engineering in suspended graphene devices for pressure sensor applications

The present paper describes a device structure for controlling and measuring strain in graphene membranes. We propose to induce strain by creating a pressure difference between the inside and the outside of a cavity covered with a graphene membrane. The combination of tight-binding calculations and a COMSOL model predicts strain induced band gaps in graphene for certain conditions and provides a guideline for potential device layouts. Raman spectroscopy on fabricated devices indicates the feasibility of this approach. Ultimately, pressure-induced band structure changes could be detected electrically, suggesting an application as ultra-sensitive pressure sensors.

Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 10(3) A cm(-2) (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.