Mikael Östling

Surface passivation oxide effects on the current gain of 4H-SiC bipolar junction transistors

Effects of surface recombination on the common emitter current gain have been studied in 4H-silicon carbide (SiC) bipolar junction transistors (BJTs) with passivation formed by conventional dry oxidation and with passivation formed by dry oxidation in nitrous oxide (N2O) ambient. A gradual reduction of the current gain was found after removal of the passivation oxide followed by air exposure. Comparison of the measurement results for two different passivated BJTs indicates that the BJTs with passivation by dry oxidation in nitrous oxide (N2O) ambient show a half order of magnitude reduction of base current, resulting in a half order of magnitude increase of current gain at low currents. This improvement of current gain is attributed to reduced surface recombination caused by reduced interface trap densities at the base-emitter junction sidewall.

Random telegraph signal noise in SiGe heterojunction bipolar transistors

In this work, random telegraph signal (RTS) noise in SiGe heterojunction bipolar transistors (HBTs) was characterized both as a function of bias voltage and temperature. The RTS amplitudes were fo ...

Investigation of thermal properties in fabricated 4H-SiC high power bipolar transistors

Abstract Silicon carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximum current gain of approximately 10 times, and a breakdown voltage of 450 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 °C, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. The device was also tested in a switched setup, showing fast turn on and turn off at 1 MHz and 300 V supply voltage. Device simulations have been used to analyze the measured data. The thermal conductivity is fitted against the self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

SiC device technology for high voltage and RF power applications

Recently, silicon carbide (SiC) has drawn considerable attention as a suitable semiconductor material for high power, high frequency, high temperature and radiation resistant devices. The commercialized substrates and the experimental device prototypes in SiC show the promises while the continued improvements in fabrication techniques are required for economically viable productions to be widespread. This paper reviews the progress and current issues in SiC device process technology and the state-of-the art SiC devices for high voltage and RF power applications.

SiC bipolar devices for high power and integrated drivers

Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. The first SiC device to reach the market was the unipolar Schottky diode. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now being offered in the voltage range up to 1.2 kV. SiC material quality and epitaxy processes have greatly improved and degradation free 100 mm wafers are readily available, which has removed one obstacle for the introduction of bipolar devices. The SiC wafer roadmap looks very favorable as volume production takes off. Other advantages of SiC are the possibility of high temperature operation (> 300 °C) and in radiation hard environments, which could offer considerable system advantages. Thanks to the mature SiC process technology, low-power integrated circuits are now also viable. Such circuits could find use in integrated drivers operating at elevated temperatures.

Low damage, highly anisotropic dry etching of SiC

A parametric study of the etching characteristics of 6H p/sup +/ and n/sup +/ SiC and thin film SiC/sub 0.5/N/sub 0.5/ in Inductively Coupled Plasma NF/sub 3//O/sub 2/ and NF/sub 3//Ar discharges has been performed. The etch rates in both chemistries increase monotonically with NF/sub 3/ percentage and rf chuck power. The etch rates go through a maximum with increasing ICP source power, which is explained by a trade-off between the increasing ion flux and the decreasing ion energy. The anisotropy of the etched features is also a function of ion flux, ion energy and atomic fluorine neutral concentration. Indium-tin-oxide (ITO) masks display relatively good etch selectivity over SiC (maximum of /spl sim/70:1), while photoresist etches more rapidly than SiC. The surface roughness of SiC is essentially independent of plasma composition for NF/sub 3//O/sub 2/ discharges, while extensive surface degradation occurs for SiCN under high NF/sub 3/:O/sub 2/ conditions.

Recent advances and issues in SiC process and device technologies

Silicon carbide (SiC) is a wide band-gap semiconductor material with potential applications for high power, high frequency, and high temperature devices. Commercially available substrates and devices together with the shown experimental prototypes show very good promises for the future while still a continued improvement in fabrication techniques and wafer substrates are required for economically viable production. The recent advances and critical issues in SiC device process technology and the current state-of-the art devices in SiC are reviewed.

Selective Epitaxial Growth with Full Control of Pattern Dependency Behavior for pMOSFET Structures

This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in pMOSPET structures. The pattern dependency behavior of tile growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by gas depletion theory of the growth species in tile stationary boundary layer over tile wafer. The control of SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a water pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

Noise and Mobility Characteristics of Bulk and Fully Depleted SOI pMOSFETs using Si and SiGe channels

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices. Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained. Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe. The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer. Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer. Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm. SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices. Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

Switching performance for fabricated and simulated 4H-SiC high power bipolar transistors

Summary form only given. In this paper, the switching performance of a SiC bipolar transistor was presented. The transistors had a static current gain of approximately 9 at room temperature. Switch frequencies up to 1 MHz and 300 V were tested with a resistive load of 1 k/spl Omega/, which the SiC BJT managed well. The breakdown voltage was around 400 V, which is 25% of the ideal breakdown voltage.