Maximilian Hofer

A microcontroller SRAM-PUF

Key storage is a well-known security issue. Usually, keys are generated and then stored in an non-volatile memory (NVM). A promising alternative are the so-called physical unclonable functions (PUFs). These functions extract key material directly from manufacturing variabilities of a device. One example of such a PUF is the SRAM-PUF. It uses the power-up states of SRAM cells to generate an ID/key. In this paper we present an SRAM PUF which we implemented on a microcontroller using the internal SRAM blocks. Combined with a simple error correction code, namely the repetition code, we could reduce the error rates to small values. Using a repetition factor of 31 we reached a probability for one or more errors within a 2048bit key of lower than 7e-7 within a temperature range from 0C to 80C. The low costs and the simplicity of implementation makes the SRAM-PUF on a microcontroller an attractive alternative to common approaches.

Using the SRAM of a Microcontroller as a PUF

In this chapter an SRAM PUF is presented that was implemented on a microcontroller using the internal SRAM block. A simple error correction scheme helps to reduce the error rate significantly. The implementation details and the measurement results are presented. Furthermore, the problems that occurred during the implementation are described. The PUF system was implemented on a NXP LPC 1768 microcontroller.

Testing and Specification of PUFs

In this chapter PUF testing and specification are described. After a short introduction, the basics to the Hamming distance and the binomial distribution is given. Then, the common parameters that are used to define the performance of PUFs are explained. This includes the mean value, the intra-chip Hamming distance, the inter-chip Hamming distance, the correlation between bits, and the power and energy consumption. By using these parameters, a useful specification of PUF circuits should be possible.

The Basic Applications

This chapter covers the three basic applications of physical unclonable functions in more detail. The first application is the identification in which the PUF is used to provide a number. This number can later be used to identify things that include a PUF. The second application is the key generation. In this case PUFs are used to provide a number that is utilized to generate a cryptographic key. It is especially important that the PUF provides a reliable output. The third and last basic application is authentication in which the PUF returns a response to an incoming challenge. Three types of authentication schemes are explained.

Parallelization of PUF Cells

In this chapter the parallelization preprocessing technique is described. This means that during an initial phase groups of PUF cells are parallelized which leads to an increase of the mismatch of such a group. Thus, the influence of noise or environmental variations can be reduced which leads to a reduction of the overall error rate. Two different parallelization types are introduced and analyzed.

PUF with Preselection

In this chapter the implementation of a two-stage latch PUF including preselection circuitry is introduced. The preselection circuit includes a binary weighted biasing block that allows for considerable error rate reduction. The implementation details and measurement results are presented. The effect of preselection is analyzed in more detail. The implementation was carried out in a 90 nm technology.

PUF with Shared Sense Amplifier

In this chapter an area reduced two-stage latch PUF is introduced. Here, the area reduction is done by sense-amplifier sharing. The implementation details and the measurement results are presented. Furthermore, the effect of the sense-amplifier sharing is analyzed in more detail. The implementation was carried out in a 90 nm technology.

Error Correction Codes

Error correction codes are an important help to ensure that the PUF provides reliable outputs. This chapter presents some information about PUF-related error correction topics. In the first part some error correction basics are provided. The second part describes different error correction codes like the Hamming code or the repetition code. In the final part PUF-specific error correction is presented. This includes an approach to a two-phase error correction scheme to handle the high error rates that are often produced by PUFs.

Refine Models for PUF Simulation Requirements

As for other analog circuits, the designer has to rely on the available transistor models during PUF design. This is especially important if the error correction implementation is also done at the same time. In this case, the error rate has to be estimated using Monte Carlo simulation. Unfortunately, the simulation often does not provide reliable results when it comes to temperature-dependent error rates. In this chapter, this problem is described in detail and a way to refine the Monte Carlo mismatch models is suggested.

Sources of Mismatch and Errors

All PUF circuits base on mismatches between different circuit components. These mismatches are utilized to generate the PUF specific output. To design a PUF it is important to know the mismatch properties of the available components. Since this work concentrates on microelectronic circuits, microelectronic components are analyzed towards their usability as PUF components in this chapter. Since MOS transistors are the major source of mismatch in microelectronic circuits, a focus is put on this kind of devices.