Mayank Shrivastava

A Tunnel FET for

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

V_{DD}

We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

Scaling Below 0.6 V With a CMOS-Comparable Performance

This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.

A Review on the ESD Robustness of Drain-Extended MOS Devices

In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate (IDDG) FinFET technology. The performance of a differential amplifier with and without the proposed CMFB scheme is compared using 2-D mixed mode device and circuit simulations. It is shown from extensive simulation results that it is possible to achieve a common mode rejection ratio of 90 dB with improved performance in terms of area, power, and bandwidth even in the presence of process variations. Stability analysis shows that the proposed CMFB scheme does not need any compensating network. The idea is validated using extensive mixed-mode circuit simulations on IDDG FinFET circuits in sub-45-nm node technologies.

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, power-delay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

We present experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metal-oxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions. Physical insight toward pulse-to-pulse instability is given. Both the current (ITLP) and time evolution of various events such as junction breakdown, parasitic bipolar triggering, and the base push-out effect are discussed in detail. Differences between the 2-D and 3-D simulation (modeling) approaches are presented, and the importance of 3-D technology-computer-aided-design-based modeling is discussed. Furthermore, a deeper physical insight toward the base push-out is given, which shows significant power dissipation due of space charge build-up, which is found at the onset of self-heating in the 2-D plane.

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Advanced mobile applications demand low power and high performance systems. In this paper, a technology computer aided design (TCAD)-based feasibility investigation of a recently proposed area tunneling field effect transistor (FET) structure is carried out from the point of high volume and ultralow power mobile applications. We demonstrate that for realization of future ultralow power and high performance systems, unique properties of area tunneling class of tunnel FET structures need to be employed. These devices are realized by engineering the tunneling region profile and tunneling cross-sectional area. The optimized devices are found to leverage up to ~ 7× energy reduction when compared with the 20-nm node MOS device options while meeting the high performance targets. Device design insights for such an area tunneling class of tunnel FET structures are discussed in this paper for the first time. It is shown that by lowering the supply voltage below 0.5 V, up to 10× reduction of the energy delay product is feasible by using area tunneling devices.

Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions

This paper demonstrates a 3D TCAD based approach towards the evaluation and pre-silicon development of nanoscale devices for advanced ESD protection concepts. Impact of various physical models and parameters on the accuracy of predicted ESD figures of merit are discussed. Moreover, various devices options, have been evaluated from 3D TCAD simulations.