Ramgopal Rao

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

Nitrogen dilution effects on structural and electrical properties of hot-wire-deposited a-SiN:H films for deep-sub-micron CMOS technologies

Hot-wire chemical vapor-deposited silicon nitride is a potential dielectric material compared to glow-discharge-deposited material due to its lower hydrogen content. In several earlier publications we have demonstrated these aspects of the HWCVD nitride. However, to replace SiO2 with a-SiN:H as the gate dielectric, this material needs further improvement. In this paper we report the results of our efforts to achieve this through nitrogen dilution of the SiH4+NH3 gas mixture used for deposition. To understand the electrical behavior of these nitride films, we characterized the films by high-frequency capacitance–voltage (HFCV) and DC J–E measurements. We attempted to evolve a correlation between the breakdown strength, as determined from the J–E curves, and aspects such as the bond density, etching rate, deposition rate and refractive index. From these correlations, we infer that nitrogen dilution of the source gas mixture has a beneficial effect on the physical and electrical properties of the hot-wire a-SiN:H films. For the highest dilution, we obtained a breakdown voltage of 12 MV cm−1.

Session 18: Characterization, reliability, and yield - Strain optimization and performance

In this session the first paper proposes a new strain mapping technique with sub-nano meter spatial resolutions using TEM. The strain maps obtained by this technique have been shown to contribute to the understanding of mobility enhancement mechanism in nano-scale MOSFETs. The second paper, which is an invited paper from UMC, provides guidelines for developing high-end strained CMOS technologies with acceptable reliability for 65 nm node and beyond. The third paper in this session shows results of IC timing and delay optimization by backside FIB processing and a comparison of the same with conventional and strained technologies. The next paper deals with defect reduction by proper plasma process optimization in order to achieve high mobility and performance improvements. The final paper in the session then addresses the variability issues in circuits by providing an understanding of high drain bias effects on threshold voltage fluctuations by an optimization of halo and drain-induced-barrier-lowering.