Mayukh Bhattacharya

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTDs) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBTs) and modulation doped field-effect transistors (MODFETs). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates.

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

This paper presents MOS-NDR, a new prototyping technique for multiple-valued logic circuits combining MOS transistors and multipeak negative differential-resistance (NDR) devices such as resonant-tunneling diodes (RTDs). MOS-NDR emulates the folded current-voltage characteristics of NDR devices such as RTDs using only NMOS transistors, MOS-NDR has enabled the development of a fully integrated multivalued signed-digit full adder (SDFA) circuit by means of a standard 0.6-micron CMOS process technology. The prototype has been fabricated and correct operation has been verified. The circuit dimensions are 123.75 by 38.7 microns, which is more than 15 times smaller than the area required by the equivalent hybrid RTD-CMOS prototype. The propagation delay of the hybrid RTD-CMOS design is estimated to be close to six times higher than that of the MOS-NDR implementation.

Augmentation of SPICE for simulation of circuits containing resonant tunneling diodes

This paper describes the incorporation of an accurate physics-based model of the resonant tunneling diode (RTD) into Berkeley SPICE version 3F5 and addresses the related direct current (dc) and transient convergence problems caused by the negative differential resistance (NDR) and the exponential nature of the device characteristics. To circumvent the de convergence problems, a new continuation technique using artificial parameter embedding and a current limiting algorithm are proposed. The studies made in this paper have shown that these techniques are superior to the in-built continuation methods of SPICE, such as Gmin-stepping and Source-stepping, for a large number of circuits of varying sizes. To improve transient convergence performance, the following three algorithms are added to SPICE: a modified forced-convergence algorithm, a new time-step adjustment algorithm, and a modified device voltage prediction algorithm.

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-/spl mu/m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 /spl mu/m/sup 2/ and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation.

A prototyping technique for large-scale RTD-CMOS circuits

In this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit.

Monolithically integrated InP-based minority logic gate using an RTD/HBT heterostructure

In this paper, we report on the design, simulation, and fabrication of an InP-based high-speed monolithically integrated minority (inverted majority) logic gate, which was implemented using an MBE-grown stacked-layer epitaxial heterostructure of a resonant-tunneling-diode (RTD) and heterojunction-bipolar-transistor (HBT). The fabricated RTDs showed a peak-to-valley current ratio of 30 at room temperature and the HBTs demonstrated a current gain of 65 and a cutoff frequency (f/sub T/) of 50 GHz. The minority logic function of the fabricated monolithic RTD-HBT gate was measured using an in-house low-frequency test setup. The detailed full-scale large-signal simulations using the NDR-SPICE simulation program predict that the integrated RTD/HBT minority logic gate can operate up to 10 GHz.

Circuit design using resonant tunneling diodes

Picosecond switching speeds and folded current voltage characteristics have made quantum tunneling devices promising alternatives for high-speed and compact VLSI circuit design. This paper describes new bistable digital logic circuit topologies that use resonant tunneling diodes (RTDs) in conjunction with heterojunction bipolar transistors (HBTs) and modulation-doped field effect transistors (MODFETs). The designed circuits include a single-gate, self-latching MAJORITY function besides basic NAND, NOR and inverter gates. The application of these circuits in the design of high-performance adders and parallel correlators is discussed. We also review multiple-valued logic (MVL) applications of RTDs that achieve significant compaction in terms of device count over comparable binary logic implementations in conventional technologies. These include a four-valued 4:1 multiplexer using 13 resonant tunneling bipolar transistors (RTBTs) and HBTs, a mask programmable four-valued, single-input gate using 4 RTDs and 14 HBTs, and a four-step countdown circuit using 1 RTD and 3 HBTs.

FD-TLM electromagnetic field simulation of high-speed III-V heterojunction bipolar transistor digital logic gates

The finite-difference transmission line matrix (FD-TLM) method allows us to model the electromagnetic behavior of a circuit based on material properties and package dimensions, without the necessity of circuit parasitic extraction. In this paper we extend the FD-TLM method to model micron-scale heterojunction bipolar transistors (HBTs) enabling us to perform time-domain, three-dimensional full-wave analysis of high-speed digital circuits containing HBTs. The accuracy of our HBT model is established by comparing with results of SPICE simulation using the modified Gummel-Poon BJT model. We present simulation results of a two-stage resistor-transistor logic (RTL) inverter chain and also a current-mode logic (CML) buffer circuit and compare the FD-TLM simulation result with SPICE. By keeping the interconnect lengths short, we ensure a fair comparison between the two simulation methods.

Convergence issues in resonant tunneling diode circuit simulation

Due to its status as the fastest switching semiconductor device and its bistable nature, the resonant tunneling diode (RTD) is considered to be one of the most promising devices for future-generation high-performance VLSI systems. However, popular circuit simulators, such as SPICE, can encounter direct current (DC) and transient convergence problems while simulating RTD-based circuits because of the negative differential resistance (NDR) in the devices current-voltage characteristics. In this paper, we study the nature of these convergence problems and provide several solution techniques that can be easily incorporated into SPICE-like circuit simulators.

Noise margins of threshold logic gates containing resonant tunneling diodes

Threshold gates consisting of RTDs in conjunction, with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and power dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.