Shriram Kulkarni

Digital circuit applications of resonant tunneling devices

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTDs) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBTs) and modulation doped field-effect transistors (MODFETs). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates.

Standard CMOS implementation of a multiple-valued logic signed-digit adder based on negative differential-resistance devices

This paper presents MOS-NDR, a new prototyping technique for multiple-valued logic circuits combining MOS transistors and multipeak negative differential-resistance (NDR) devices such as resonant-tunneling diodes (RTDs). MOS-NDR emulates the folded current-voltage characteristics of NDR devices such as RTDs using only NMOS transistors, MOS-NDR has enabled the development of a fully integrated multivalued signed-digit full adder (SDFA) circuit by means of a standard 0.6-micron CMOS process technology. The prototype has been fabricated and correct operation has been verified. The circuit dimensions are 123.75 by 38.7 microns, which is more than 15 times smaller than the area required by the equivalent hybrid RTD-CMOS prototype. The propagation delay of the hybrid RTD-CMOS design is estimated to be close to six times higher than that of the MOS-NDR implementation.

CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices

This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-/spl mu/m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 /spl mu/m/sup 2/ and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation.

A prototyping technique for large-scale RTD-CMOS circuits

In this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit.

Circuit design using resonant tunneling diodes

Picosecond switching speeds and folded current voltage characteristics have made quantum tunneling devices promising alternatives for high-speed and compact VLSI circuit design. This paper describes new bistable digital logic circuit topologies that use resonant tunneling diodes (RTDs) in conjunction with heterojunction bipolar transistors (HBTs) and modulation-doped field effect transistors (MODFETs). The designed circuits include a single-gate, self-latching MAJORITY function besides basic NAND, NOR and inverter gates. The application of these circuits in the design of high-performance adders and parallel correlators is discussed. We also review multiple-valued logic (MVL) applications of RTDs that achieve significant compaction in terms of device count over comparable binary logic implementations in conventional technologies. These include a four-valued 4:1 multiplexer using 13 resonant tunneling bipolar transistors (RTBTs) and HBTs, a mask programmable four-valued, single-input gate using 4 RTDs and 14 HBTs, and a four-step countdown circuit using 1 RTD and 3 HBTs.

A high-speed 32-bit parallel correlator for spread spectrum communication

This paper describes a high speed 32-bit pipelined digital parallel correlator implemented in a Lattice field programmable gate array (FPGA). The parallel correlator is of use in CDMA and spread spectrum transceivers for the continuous calculation of correlation between an incoming data stream with a PN sequence. The maximum frequency of operation of the FPGA based correlator is 87 MHz providing a throughput of one 32-bit correlation every 11.5 ns resulting in considerable improvement over commercially available correlators in terms of speed as well as number of bits. The high speed of operation of the correlator coupled with its ability to handle up to 32 chips per data bit alleviates the problem of low information bit rates due to signal encoding in spread spectrum communication systems. A CMOS integrated circuit implementation of the parallel correlator is presented.