Keivan Etessam-Yazdani

Modeling and Data for Thermal Conductivity of Ultrathin Single-Crystal SOI Layers at High Temperature

Simulations of the temperature field in silicon-on-insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This paper develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers and presents the experimental data for 50-nm-thick single-crystal silicon layers at high temperatures. The model applies to the temperature range of 300-1000 K for silicon layer thicknesses from 10 nm to 1 mum (and even bulk), which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration

Impact of Power Granularity On Chip Thermal Modeling

In this paper we investigate the impact of the granularity of the power distribution for accurately predicting semiconductor chip temperature fields. Specifically, we calculate the transfer functions between power distributions and resulting temperature maps for various microprocessor packages and cooling conditions, which establish a minimum granularity required for accurate thermal analysis. The purpose of this paper is twofold: first, we like to provide some general guidelines for the impact of different power granularities on the global chip temperatures and second we intend to spike a broader discussion about to which extent small heating effects can affect chip temperatures for circuits under full operation. As such this work is not only beneficial for package and cooling solution engineering but also important to circuit designers and computer architects in their battle against hotspots in microprocessors

Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis

In this paper, we investigate the impact of the granularity of the power distribution for accurately predicting semiconductor chip temperature fields. Specifically, we calculate the transfer functions between power distributions and resulting temperature maps for various microprocessor packages and cooling conditions, which establish a minimum granularity required for accurate thermal analysis. The purpose of this paper is twofold: First, we like to provide some general guidelines for the impact of different power granularities on the global chip temperatures and second we intend to spike a broader discussion about to which extent small heating effects can affect chip temperatures for circuits under full operation. As such this work is not only beneficial for package and cooling solution engineering but is also important to circuit designers and computer architects in their battle against hotspots in microprocessors.

Ballistic phonon transport and self-heating effects in strained-silicon transistors

In this manuscript, different aspects of nanoscale thermal transport in strained silicon transistors will be addressed. The two-dimensional Boltzmann transport equations for phonons in Si and SiGe alloy layers, along with the acoustic mismatch model for the interface, are used to capture the sub-continuum heat conduction effects in the device. It is shown that the lateral thermal conductivity of a 10-nm strained-Si layer grown on the SiGe underlayer can vary from 14 to 20W/m-K, depending on the interface specularity parameter. The resulting temperature distribution in the device is used to predict the impact of self-heating on performance of future generations of strained-Si devices. The analysis shows that the merits of strained-Si technology can be suppressed by excessive self-heating; therefore, additional considerations in the design of these devices need to be taken into account

Modeling of Localized Heating Effect in Sub-Micron Silicon Transistors

The performance and reliability of sub-micron semiconductor transistors demands accurate modeling of electron and phonon transport at nanoscales. The continued downscaling of the critical dimensions, introduces hotspots, inside transistors, with dimensions much smaller than phonon mean free path. This phenomenon, known as localized heating effect, results in a relatively high temperature at the hotspot that cannot be predicted using heat diffusion equation. While the contribution of the localized heating effect to the total device thermal resistance is significant during the normal operation of transistors, it has even greater implications for the thermoelectrical behavior of the device during an electrostatic discharge (ESD) event. The Boltzmann transport equation (BTE) can be used to capture the ballistic phonon transport in the vicinity of a hot spot but many of the existing solutions are limited to the one-dimensional and simple geometry configurations. We report our initial progress in solving the two dimensional Boltzmann transport equation for a hot spot in an infinite media (silicon) with constant temperature boundary condition and uniform heat generation configuration.Copyright

Sub-continuum thermal analysis of strained-Si/SiGe transistor scaling

The paper focuses on the effect of nano-scale thermal phenomena on the performance of strained-Si transistors. The impact of SiGe underlayer and interface roughness on the lateral thermal conductivity of the transistor channel at room temperature is studied. The experimental data and predictions for thin Si layer thermal conductivity and the solutions of the Boltzmann transport equations (BTE) for phonon transport in the strained-Si/SiGe bilayer configuration are used to estimate the effect of self-heating on some of the key parameters of future generations of strained-Si transistors. The analysis presented shows that, due to the continuous increase of self-heating in the future, the merits of strained-Si transistors will be suppressed, unless various parameters involved in the design of these devices are revised to maintain the existing merits.

Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. Effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated into a electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of gate length and silicon layer thickness. The device thermal resistance is increased by nearly a factor of 3 due to the scaling of gate length from 180nm to 10nm. Self-heating in SOI devices with gate length of 10nm can be responsible for up to 30% reduction in the saturation current and neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two.Copyright

Spatial Frequency Domain Analysis of Heat Transfer in Microelectronic Chips With Applications to Temperature Aware Computing

In this paper we present a novel analytical approach for obtaining the thermal transfer function of multi-layer chips in the spatial frequency domain. The behavior of the transfer function is used to address a number of key issues such as 1) the appropriate power granularity required for microarchitecture thermal-power analysis, and 2) the impact of packaging and cooling solutions on heat removal from chip hotspots. The merit of the presented method is in 1) simplicity, such that even for rather complicated multi-layer structures the analysis takes only a fraction of a second, and 2) accuracy, because the approach is based on the exact solution of three-dimensional heat diffusion equations.© 2007 ASME

Impact of Scaling on Thermal Behavior of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. For the first time the effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated to the hydrodynamic simulation of electrons and holes in a commercial electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of the gate length and silicon layer thickness. The device thermal resistance is increased by more than a factor of 2 due to the scaling of gate length from 180nm to 45nm. Neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two. Thermal resistance of SOI devices with 25nm silicon layer can be up to 8 times larger than that of bulk devices

Experimental Investigation of Scaling Effect on Thermal Transport in Nanoscale Hot Spots

This article reports experimental investigation of the scaling effect on thermal transport in platinum nanoheaters deposited on a single crystalline silicon substrate. The size dependency of the thermal resistances of nanoheaters with dimensions from 5 μm down to 100 nm was experimentally obtained. Additional joule heating and electrical resistance thermometry in heater/sensor pairs of various dimensions and spacing (100 to 400 nm) were carried out in order to study the temperature distribution in the vicinity of these nanoheaters. The results of these two sets of measurements confirm that the thermal resistances of smaller nanoheaters are dominated by the interface resistance between the platinum and silicon substrate. Furthermore, analytical solutions of the BTE around a hot spot were used to evaluate and examine the significance of the localized heating or subcontinuum transport around a hot spot.