Mehrez Marzougui

Preliminary study of block matching algorithms for wavelet-based t+2D video coding

In recent years, video compression has emerged as an effective technique to reduce spatial and temporal redundancy in video sequence. Temporal redundancy reduction deals with motion estimation (ME) and motion compensation (MC) algorithm with the matching technique to produce the next encoded video frame with motion vector. Motion estimation is the process of determining the movement of blocks between adjacent video frames by which image information is assessed for similarities that can be reused in subsequent frames. However, computational complexity and resource sharing of the motion estimation algorithm poses great challenges for real time applications. Fast search algorithms emerged as important search technique to achieve real time tracking results. Among the different motion estimation algorithms block matching is the most common used technique. This paper presents a system-level implementation of a wavelet-based H2D video coding. Three block matching motion estimation algorithms are implemented in order to evaluate the overall system performance. In fact, since the chip design and layout process is time consuming and expensive, it is very important to be able to predict the overall system performance in a high-level implementation before its circuit layout is deployed. The aim is to discuss the impact of different block matching motion estimation algorithms on video coding performance. Because of the complexity of the entire motion estimation system, decision in choosing one algorithm versus the other algorithms is often empirical and crucial.

G729 Voice Decoder Design

Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part—the autocorrelation computation—using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13 Kbit/s, APC 9.6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation.

Efficient implementation of a real-time lane departure warning system

Because of the increasing number of population of vehicles, the road traffic accidents are becoming more and more serious in recent years. Hence, improving driver assistance systems for security has become an important area of research. This paper presents a robust lane detection and tracking system based on monocular vision. We use the Lane Departure Warning (LDW) systems to detect the position of the vehicle with respect to the lane boundary. An algorithm to detect the road lane marking and to control the direction of the vehicle is proposed. Our work consists in establishing a Region Of Interest (ROI) of the road images, data pre-processing using the Gaussian filter and then apply the Canny edge detector to enhance lane boundaries. A method to extract lane boundaries based on color information and image segmentation by using the histogram threshold, Hough transform is proposed, and the current vehicle position is obtained. In such a case, we can decide if the vehicle is doing lane departure used on the vehicles position, the system sends a warning message to the driver. Our proposed algorithm works accurately with various lighting conditions as well as on different road types.

High-level implementation of Video compression chain coding based on MCTF lifting scheme

Due to their multiresolution signal decomposition, wavelet analysis has shown great success in the analysis of signals such as image processing and video coding. The recent progress in 3D spatio-temporal wavelet video coding led to the emergence of a new generation of scalable video schemes. In fact, much attention has been given to t+2D analysis where temporal redundancy is first exploited through a motion compensated multiresolution decomposition and the resulting temporal subband frames are then spatially decomposed with a wavelet transform. This paper presents a high-level implementation of a video coding chain based on MCTF temporal filtering and spatial block processing. In order to evaluate the overall system performance, a comparative study was conducted to choose the adequate block-matching algorithm during the temporal filtering steps. Evaluation of the quality of the reconstructed frames based on the compression ratio was done with spatial analysis based on 5/3 and 9/7 wavelet. Simulation results show that the proposed video coding has a notable performance in terms of compression ratio and quality, also some advantages provided by the choice of the temporal-filtering equation allow to reduce the computational complexity and reduce the amount of memory occupied during the video encoding/decoding process compared to classical temporal 5/3MCTF filtering.

Co-simulation and communication synthesis approach for intellectual properties based SoCs

This paper presents an approach to integrate intellectual properties (IPs) based systems on chip (SoCs). The aim is to synthesize communication units using co-simulation environment and a stochastic process. The proposed approach allows to bound communication memories for different loading rates of the master processor. According to the chosen communication unit while interconnecting IPs components, this approach also allows to refine communication structures in order to lead to a model easily mappable onto the target architecture. The approach has been experimented and validated through a detailed case study concerning the verification and the integration of the discrete and direct wavelet transform (DDWT) IP in a mixed hardware/software architecture. Software partitions are executed on the ARM7 processor and hardware partitions are executed on the ModelSim simulator. The used co-simulation tool is Seamless CVE(TM) of Mentor Graphics. A library of adaptation protocols of IP blocs to the environment as well as a set of standard communication units (RAM, DPRAM, FIFOs) have been also developed and used.

Evaluation of the performance of block matching algorithms in wavelet-based t+2D video coding

Motion estimation is the process of determining the movement of blocks between adjacent video frames by which image information is assessed for similarities that can be reused in subsequent frames. However, computational complexity and resource sharing of the motion estimation algorithm poses great challenges for real time applications. Fast search algorithms emerged as important search technique to achieve real time tracking results. Among the different motion estimation algorithms block matching is the most common used technique. This paper presents a system-level implementation of a wavelet-based t+2D video coding. Three block matching motion estimation algorithms are implemented in order to evaluate the overall system performance. In fact, since the chip design and layout process is time consuming and expensive, it is very important to be able to predict the overall system performance in a highlevel implementation before its circuit layout is deployed. The aim is to discuss the impact of different block matching motion estimation algorithms on video coding performance. Because of the complexity of the entire motion estimation system, decision in choosing one algorithm versus the other algorithms is often empirical and crucial.