Mohamed Atri

Definition and Performance Evaluation of a Robust SVM Based Fall Detection Solution

We propose an automatic approach to detect falls in home environment. A Support Vector Machine based classifier is fed by a set of selected features extracted from human body silhouette tracking. The classifier is followed by filtering operations taking into account the temporal nature of a video. The features are based on height and width of human body bounding box, the users trajectory with her/his orientation, Projection Histograms and moments of order 0, 1 and 2. We study several combinations of usual transformations of the features (Fourier Transform, Wavelet transform, first and second derivatives), and we show experimentally that it is possible to achieve high performance using a single camera.We evaluated the robustness of our method using a realistic dataset. Experiments show that the best tradeoff between classification performance and time processing result is obtained combining the original data with their first derivative. The global error rate is lower than 1%, and the recall, specificity and precision are high (respectively 0.98, 0.996 and 0.942). The resulting system can therefore be used in a real environment. Hence, we also evaluated the robustness of our system regarding location changes. We proposed a realistic and pragmatic protocol which enables performance to be improved by updating the training in the current location, with normal activities records.

Optimized spatio-temporal descriptors for real-time fall detection: comparison of support vector machine and Adaboost-based classification

Abstract. We propose a supervised approach to detect falls in a home environment using an optimized descriptor adapted to real-time tasks. We introduce a realistic dataset of 222 videos, a new metric allowing evaluation of fall detection performance in a video stream, and an automatically optimized set of spatio-temporal descriptors which fed a supervised classifier. We build the initial spatio-temporal descriptor named STHF using several combinations of transformations of geometrical features (height and width of human body bounding box, the user’s trajectory with her/his orientation, projection histograms, and moments of orders 0, 1, and 2). We study the combinations of usual transformations of the features (Fourier transform, wavelet transform, first and second derivatives), and we show experimentally that it is possible to achieve high performance using support vector machine and Adaboost classifiers. Automatic feature selection allows to show that the best tradeoff between classification performance and processing time is obtained by combining the original low-level features with their first derivative. Hence, we evaluate the robustness of the fall detection regarding location changes. We propose a realistic and pragmatic protocol that enables performance to be improved by updating the training in the current location with normal activities records.

An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM

Fourier Descriptors (FD) can be used as feature vector components in various applications, such as real-time color object recognition or image retrieval. The full process is composed of the feature extraction followed by a classification step performed using support vector machine (SVM). In order to accelerate the computation of FD, a hardware implementation using FPGA technology is presented in this paper. We evaluated classification performance with respect to lighting variations and noise sensibility. Several experiments were carried out on three databases. Then an efficient architecture for FD computation on FPGAs is proposed and designed as accelerator. The WildCard is used to prototype this implementation. This design can have an operation speed up of approximately 10 compared to the standard software PC implementation.

Real time hardware co-simulation of Edge Detection for video processing system

A methodology for implementing real-time DSP applications on a field programmable gate arrays (FPGA) using Xilinx System Generator (XSG) for Matlab is presented in this paper. It presents architecture for Edge Detection using Sobel Filter for image processing using Xilinx System Generator. The design was implemented targeting a Spartan3A DSP 3400 device (XC3SD3400A-4FGG676C) then a Virtex 5 (xc5vlx50-1ff676). The Edge Detection method has been verified successfully with no visually perceptual errors in the resulted images.

An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution,etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. To reach this goal, we propose in this paper a flexible hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search as well as variable block size to be selected and adjusted. Hence, this novel architecture, especially designed for FPGA targets, proposes high-speed processing for a configuration which supports the variable size blocks and quarter-pel refinement, as described in H.264. The proposed low-cost architecture based on Virtex 6 FPGA can process integer motion estimation on 1080 HD video streams, respectively, at 13 fps using full search strategy (108k Macroblocks/s) and up to 223 fps using diamond search (1.8M Macroblocks/s). Moreover subpel refinement in quarter-pel mode is performed at 232k Macroblocks/s.

Embedded real-time video processing system on FPGA

Image Processing algorithms implemented in hardware have emerged as the most viable solution for improving the performance of image processing systems. The introduction of reconfigurable devices and high level hardware programming languages has further accelerated the design of image processing in FPGA. This paper briefly presents the design of Sobel edge detector system on FPGA. The design is developed in System Generator and integrated as a dedicated hardware peripheral to the Microblaze 32 bit soft RISC processor with the EDK embedded system. The input comes from a live video acquired from a CMOS camera and the detected edges are displayed on a DVI display screen.

Using Xilinx System Generator for Real Time Hardware Co-simulation of Video Processing System

The use of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator becomes increasingly important because of time-to-market constraints. This paper presents a methodology for implementing real-time DSP applications on a reconfigurable logic platform using Xilinx System Generator (XSG) for Matlab. The methodology aims to improve the design verfication efficiency for such complex system. It presents architecture for Color Space Conversion (CSC) RGBTOYCbCr for video processing using Xilinx System Generator. The design was implemented targeting a Spartan3 device (3S200PQ208) then a Virtex II Pro (xc2vp7–6ff672). Obtained results are discussed and compared with an other architecture. The conversion method has been verified successfully with no visually perceptual errors in the transformed images.

Optimized parallel implementation of face detection based on GPU component

Display Omitted An algorithm for face detection has been implemented on CPU.An acceleration of this algorithm on GPU migration.Performance of GPU implementation shows the effectiveness of this implementation.Another optimization method on GPU are operated. Face detection is an important aspect for various domains such as: biometrics, video surveillance and human computer interaction. Generally a generic face processing system includes a face detection, or recognition step, as well as tracking and rendering phase. In this paper, we develop a real-time and robust face detection implementation based on GPU component. Face detection is performed by adapting the Viola and Jones algorithm. We have developed and designed optimized several parallel implementations of these algorithms based on graphics processors GPU using CUDA (Compute Unified Device Architecture) description.First, we implemented the Viola and Jones algorithm in the basic CPU version. The basic application is widened to GPU version using CUDA technology, and freeing CPU to perform other tasks. Then, the face detection algorithm has been optimized for the GPU using a grid topology and shared memory. These programs are compared and the results are presented. Finally, to improve the quality of face detection a second proposition was performed by the implementation of WaldBoost algorithm.

Human detection based on integral Histograms of Oriented Gradients and SVM

This paper presents a method for human detection in video sequence. The Histogram of Oriented Gradients (HOG) descriptors show experimentally significantly out-performs existing feature sets for human detection. Because of HOG computation influence on performance, we finally choose a more better HOG descriptor to extract human feature from visible spectrum images based on OpenCv and MS VC++. We realized an image descriptor based on Integral Histograms of Oriented Gradients (HOG), associated with a Support Vector Machine (SVM) classifier and evaluate its efficiency.

Design of a 2D Mesh-Torus Router for Network on Chip

New systems on chip (SoC) design allow one to build heterogeneous systems with several functional units, distributed memories, and interconnections on the same chip. In order to achieve more reuse, flexibility, and performance, bus based interconnections are no more sufficient and Network on Chip concepts are emerged. This paper presents the design of a scalable packet based router allowing data transfer and managing dynamically several communications in parallel. The designed router, described in VHDL on RTL level, was simulated in the case of topologies 2D- mesh and 2D-torus (2x2), (3x3) and then (4x4). The used design methodology is based on VHDL as a description language, simulation and synthesis tools.