Melanie Elm

Scan chain clustering for test power reduction

An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.

Structural In-Field Diagnosis for Random Logic Circuits

In-field diagnosability of electronic components in larger systems such as automobiles becomes a necessity for both customers and system integrators. Traditionally, functional diagnosis is applied during integration and in workshops for in-field failures or break-downs. However, functional diagnosis does not yield sufficient coverage to allow for short repair times and fast reaction on systematic failures in the production. Structural diagnosis could yield the desired coverage, yet recent built-in architectures which could be reused in the field either do not reveal diagnostic information or necessitate dedicated test schemes. The paper at hand closes this gap with a new built-in test method for autonomous in-field testing and in-field diagnostic data collection. The proposed Built-In Self-Diagnosis method (BISD) is based on the standard BIST architecture and can seamlessly be integrated with recent, commercial DfT techniques. Experiments with industrial designs show that its overhead is marginal and its structural diagnostic capabilities are comparable to those of external diagnosis on high-end test equipment.

Structural Test for Graceful Degradation of NoC Switches

Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is increased at the cost of reduced performability. In this paper, a new diagnosis method based on the standard flow of industrial volume testing is presented, which is able to identify the intact functions rather than providing only a pass/fail result for the complete switch. The new method combines for the first time the precision of structural testing with information on the functional behavior in the presence of defects to determine the unaffected switch functions and use partially defective NoC switches. According to the experimental results, this improves the performability of NoCs as more than 61\% of defects only impair one switch port. Unlike previous methods for implementing fault tolerant switches, the developed technique does not impose any additional area overhead and is compatible with any switch design.

BISD: scan-based built-in self-diagnosis

Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may be necessary to apply additional deterministic patterns, which cause additional hardware costs. Secondly, the BIST-signature reveals only poor diagnostic information. Recently, the first issue has been addressed successfully. The paper at hand proposes a viable, effective and cost efficient solution for the second problem.

Scan chain organization for embedded diagnosis

Keeping diagnostic resolution as high as possible while maximizing the compaction ratio is subject to research since the advent of embedded test. In this paper, we present a novel scan design methodology to maximize diagnostic resolution when compaction is employed. The essential idea is to consider the diagnostic resolution during the clustering of scan elements to scan chains. Our methodology does not depend on a fault model and is helpful with any type of compactor. A linear time heuristic is presented to solve the scan chain clustering problem. We evaluate our approach for industrial and academic benchmark circuits. It turns out to be superior to both random and to layout driven scan chain clustering. The methodology is applicable to any gate-level design and fits smoothly into an industrial design flow.

Accurate X-Propagation for Test Applications by SAT-Based Reasoning

Unknown or X-values during test applications may originate from uncontrolled sequential cells or macros, from clock or A/D boundaries, or from tristate logic. The exact identification of X-value propagation paths in logic circuits is crucial in logic simulation and fault simulation. In the first case, it enables the proper assessment of expected responses and the effective and efficient handling of X-values during test response compaction. In the second case, it is important for a proper assessment of fault coverage of a given test set and consequently influences the efficiency of test pattern generation. The commonly employed n-valued logic simulation evaluates the propagation of X-values only pessimistically, i.e., the X-propagation paths found by n -valued logic simulation are a superset of the actual propagation paths. This paper presents an efficient method for overcoming this pessimism and for determining accurately the set of signals that carry an X-value for an input pattern. As examples, it investigates the influence of this pessimism on the two applications, X-masking and stuck-at fault coverage assessment. The experimental results on benchmark and industrial circuits assess the pessimism of classic algorithms and show that these algorithms significantly overestimate the signals with X-values. The experiments show that overmasking of test data during test compression can be reduced by an accurate analysis. In stuck-at fault simulation, the coverage of the test set is increased by the proposed algorithm without incurring any overhead.

On Determining the Real Output Xs by SAT-Based Reasoning

Embedded testing, built-in self-test and methods for test compression rely on efficient test response compaction. Often, a circuit under test contains sources of unknown values (X), uninitialized memories for instance. These X values propagate through the circuit and may spoil the response signatures. The standard way to overcome this problem is X-masking. Outputs which carry an X value are usually determined by logic simulation. In this paper, we show that the amount of Xs is significantly overestimated, and in consequence outputs are over masked, too. An efficient way for the exact computation of output Xs is presented for the first time. The resulting X-masking promises significant gains with respect to test time, test volume and fault coverage.

Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs

The automotive industry has to deal with an increasing amount of electronics in todays vehicles. This paper describes the advantages of structural tests during in-field system test, reusing existing test data and on-chip structures. Demonstration is the embedded test of an ASIC within an automotive control unit, utilizing manufacturing scan-tests.

Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen

In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden Komponenten an den Herstellungskosten mechatronischer Systeme rapide zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15% des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits uber 60% [8.9], wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen zuruckzufuhren. Sehr deutlich ist diese Zunahme im Automobil zu beobachten. Wahrend das Antiblockiersystem und die digitale Motorsteuerung schon seit Jahren zum Standard gehoren, werden nun zunehmend auch Fahrerassistenz- und Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu verschwimmen. Die Bandbreite moglichen Fehlverhaltens reicht vom Ausfall des Navigationssystems uber Storungen der Zentralverriegelung bis hin zum automatischen Einleiten von Bremsmanovern bei hohen Geschwindigkeiten. Entsprechend ergeben sich hier hohe Anforderungen an die Zuverlassigkeit dieser Systeme.