James E. Chung

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFETs is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries. >

Analysis and decomposition of spatial variation in integrated circuit processes and devices

Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation; spline- and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.

Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance

This paper contributes the first study of manufacturing variation on interconnect timing performance in a high speed microprocessor. Also new in this paper is a methodology using timing analysis in conjunction with post-extraction net adjustment to account for interconnect structure variation (e.g., that arising due to pattern dependencies); this methodology is efficient enough to enable thousands of nets to be analyzed for variation and is compatible with current CAD tools.

An integrated characterization and modeling methodology for CMP dielectric planarization

Efficient chip-level CMP models are required to predict dielectric planarization performance for arbitrary layouts prior to CMP. We present an integrated calibration and modeling methodology for oxide planarization which extends previous work in several important ways. First, we describe improved characterization methods for model calibration, including new short flow test masks and simplified planarization model parameter extraction. Secondly, we present efficient physically motivated density calculation and integration with a planarization model for prediction of oxide thickness above and between metal structures across the entire die. Predictions based on the model show excellent agreement when applied to layouts not used in model calibration.

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFETs are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 /spl mu/m regime may favor partially depleted devices.<<ETX>>

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFETs to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.<<ETX>>

Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET lifetime prediction

The device degradation of oxide-spacer LDD NMOSFETs due to hot carriers is studied in detail. The observed saturation in the degradation time dependence is found to be due to a combination of an increase in the series resistance in the lightly doped drain region, and a reduction of the carrier mobility in the channel and subdiffusion regions. The increase in series resistance eventually saturates. Thus, a more accurate and consistent value of LDD NMOSFET lifetime can be determined using extrapolations which are based on the asymptotic value of the degradation rate coefficient. >

Physics and technology of ultra short channel MOSFET devices

It is pointed out that, as MOSFET channel lengths are scaled below about 0.15 mu m, nonstationary carrier transport effects become increasingly important. These effects can result in increased drain current over what is expected from stationary transport theory (i.e. velocity saturation), and in decreased hot-carrier energy spectrum spread, or carrier temperature, leading to improved device reliability. However, the magnitude of these effects depends strongly not only on channel length but also on overall device design such as channel doping configuration, drain junction depth, etc. Besides minimization of junction depths, optimal device design requires a super-steep-retrograde channel doping, with surface doping concentration no higher than mid-10/sup 16/ cm/sup -3/. This can be achieved with indium doping for NMOS, and antimony or arsenic doping for PMOS extreme submicron transistors.<<ETX>>

Use of short-loop electrical measurements for yield improvement

Modern submicron processes are more sensitive to both random and systematic wafer-level process variation than ever before. Given the dimensional control limitations of new technologies, the amount of wafer-to-wafer and within wafer nonuniformity of many steps is becoming a significant fraction of the total error budget, which already includes the usual step-to-step allocations. However, a significant portion of the total observed variability is systematic in nature. Accordingly, particle defects may not continue to dominate parametric yield loss without improved understanding of parametric variations. In this paper, we demonstrate the use of short-loop electrical metrology to carefully characterize and decouple wafer-level variability of several critical processing steps. More specifically, we present our method and give results obtained from variability analyses for lithography critical dimension (CD) and inter-level dielectric (ILD) thickness control. Using statistically designed experiments and dedicated test structures, the main factors affecting dielectric thickness variability has been identified. The systematic variability from a wafer stepper has been extracted using a physically based statistical data filter. Once isolated, the deterministic variability can be modeled and controlled to enhance process and circuit design for manufacturability (DFM). We hope that in the future this work will be coupled with novel DFM-oriented CAD tools that encapsulate this information in a fashion that makes it useful to process and circuit designers. >