Melik Yazici

Wide Range, Process and Temperature Compensated Voltage Controlled Current Source

This paper presents a wide range, voltage controlled-current source circuit that is optimized to compensate for both process and temperature variations. Compensation for process variations is realized by cancellation of the threshold voltage variations. Temperature compensation is applied by the use of a poly resistor. Ninety samples from 3 different chips of the same wafer run were measured, and for the nominal value of 25 nA, current sources have a standard deviation of 1.22% (4.8 × improvement over an uncompensated current reference). The simulated standard deviation is 8%, resulting a simulated improvement factor of 8×, when samples from different wafer runs are to be measured. Measured temperature drift is 250 ppm/°C for a temperature range of 0-80°C. For the mentioned performance, the circuit consists of only 7 components occupying an area of 64 μm × 91 μm, using AMS 0.35 μm, 5 V CMOS process technology. The new current source is used to mimic the behavior of an infrared detector, which creates current in the range of 1-50 nA. A modified version of proposed current source is also designed with no off-chip bias voltages, and has a temperature coefficient of 57 ppm°C for 9 nA with an acceptable process compensation.

Design of a ROIC for Scanning Type HgCdTe LWIR Focal Plane Arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

A fully digital readout employing extended counting method to achieve very low quantization noise

This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 200 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32x32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Simulation results are given for complete readout.

Design of monocrystalline Si/SiGe multi-quantum well microbolometer detector for infrared imaging systems

This paper presents the design, modelling and simulation results of silicon/silicon-germanium (Si/SiGe) multi-quantum well based bolometer detector for uncooled infrared imaging system. The microbolometer is designed to detect light in the long wave length infrared (LWIR) range from 8 to 14 μm with pixel size of 25 x 25 μm. The design optimization strategy leads to achieve the temperature coefficient of resistance (TCR) 4.5%/K with maximum germanium (Ge) concentration of 50%. The design of microbolometer entirely relies on standard CMOS and MEMS processes which makes it suitable candidate for commercial infrared imaging systems.

Implementation of pixel level digital TDI for scanning type LWIR FPAs

Implementation of a CMOS digital readout integrated circuit (DROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels with over sampling rate of 3. Analog signal integrated on integration capacitor is converted to digital domain in pixel, and digital data is transferred to TDI summation counters, where contributions of 8 pixels are added. Output data is 16 bit, where 8 bits are allocated for most significant bits and 8 bits for least significant bits. Control block of the ROIC, which is responsible of generating timing diagram for switches controlling the pixels and summation counters, is realized with VerilogHDL. Summation counters and parallel-to-serial converter to convert 16 bit parallel output data to single bit output are also realized with Verilog HDL. Synthesized verilog netlists are placed&routed and combined with analog under-pixel part of the design. Quantization noise of analog-to-digital conversion is less than 500e-. Since analog signal is converted to digital domain in-pixel, inaccuracies due to analog signal routing over large chip area is eliminated. ROIC is fabricated with 0.18μm CMOS process and chip area is 10mm2. Post-layout simulation results of the implemented design are presented. ROIC is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electron, while power consumption is less than 30mW. ROIC is designed to perform in cryogenic temperatures.

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Design of ROIC Based on Switched Capacitor TDI for MCT LWIR Focal Plane Arrays

Design and measurement of a silicon readout integrated circuit (ROIC) based on switched capacitor time delay integration (TDI) technique for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality for scanning type of detector by using switched capacitor technique with a supersampling rate of three, increasing SNR and the spatial resolution. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time, 5 gain settings at the input and auto gain adjustment with pixel deselection capability. Programming can be done parallel or serially with test mode functionality. ROIC can handle up to 3.75V dynamic range with the load being 25pF capacitive, output settling time is less than 80 nsec. This low power ROIC consumes less than 100mW. Moreover, input referred noise is less than 750 rms electrons. Simulations and measurements are done in both room temperature and cryogenic (77 °K) temperatures. In order to measure and simulate chip without a detector, process and temperature invariant current source block that imitate detector currents are designed as well. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

A low-power CMOS readout IC with on-chip column-parallel SAR ADCs for microbolometer applications

A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (~1M Ω) and higher TCR values (~%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17x17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process.

A low-power CMOS readout IC design for bolometer applications

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

A PFM-based MWIR DROIC employing off-pixel fine conversion of photocharge to digital using integrated column ADCs

A 32x32 prototype of a digital readout IC (DROIC) for medium-wave infrared focal plane arrays (MWIR IR-FPAs) is presented. The DROIC employs in-pixel photocurrent to digital conversion based on a pulse frequency modulation (PFM) loop and boasts a novel feature of off-pixel residue conversion using 10-bit column SAR ADCs. The remaining charge at the end of integration in typical PFM based digital pixel sensors is usually wasted. Previous works employing in-pixel extended counting methods make use of extra memory and counters to convert this left-over charge to digital, thereby performing fine conversion of the incident photocurrent. This results in a low quantization noise and hence keeps the readout noise low. However, focal plane arrays (FPAs) with small pixel pitch are constrained in pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this work, a novel approach to measure the residue outside the pixel using column -parallel SAR ADCs has been proposed. Moreover, a modified version of the conventional PFM based pixel has been designed to help hold the residue charge and buffer it to the column ADC. In addition to the 2D array of pixels, the prototype consists of 32 SAR ADCs, a timing controller block and a memory block to buffer the residue data coming out of the ADCs. The prototype has been designed and fabricated in 90nm CMOS.