Shahbaz Abbasi

Physical device modeling of Si/Si1-xGex multi-quantum well detector to optimize Ge content for higher thermal sensitivity

This paper presents the physical device modeling of a Si/Si1-xGex multi-quantum well (MQW) detector to optimize the Ge content in the Si/Si1-xGex well required to enhance thermal sensitivity for a potential microbolometer application. The modeling approach comprises a self-consistent coupled Poisson-Schroedinger solution in series with the thermionic emission theory at the Si/Si1-xGex heterointerface and quantum confinement within the Si/Si1-xGex MQW. The integrated simulation environment developed in Sentauruas WorkBench (SWB) TCAD is employed to investigate the transfer characteristics of the device consisting three stacks of Si/Si1-xGex wells with an active area of 17μm x 17μm were investigated and compared with experiment data.

A low-power CMOS readout IC design for bolometer applications

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

A PFM-based MWIR DROIC employing off-pixel fine conversion of photocharge to digital using integrated column ADCs

A 32x32 prototype of a digital readout IC (DROIC) for medium-wave infrared focal plane arrays (MWIR IR-FPAs) is presented. The DROIC employs in-pixel photocurrent to digital conversion based on a pulse frequency modulation (PFM) loop and boasts a novel feature of off-pixel residue conversion using 10-bit column SAR ADCs. The remaining charge at the end of integration in typical PFM based digital pixel sensors is usually wasted. Previous works employing in-pixel extended counting methods make use of extra memory and counters to convert this left-over charge to digital, thereby performing fine conversion of the incident photocurrent. This results in a low quantization noise and hence keeps the readout noise low. However, focal plane arrays (FPAs) with small pixel pitch are constrained in pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this work, a novel approach to measure the residue outside the pixel using column -parallel SAR ADCs has been proposed. Moreover, a modified version of the conventional PFM based pixel has been designed to help hold the residue charge and buffer it to the column ADC. In addition to the 2D array of pixels, the prototype consists of 32 SAR ADCs, a timing controller block and a memory block to buffer the residue data coming out of the ADCs. The prototype has been designed and fabricated in 90nm CMOS.

A PFM-Based Digital Pixel With an Off-Pixel Residue Measurement for Small Pitch FPAs

Digital pixels based on pulse frequency modulation employ counting techniques to achieve a very high charge-handling capability compared to their analog counterparts. Moreover, extended counting methods that make use of leftover charge (residue) on the integration capacitor help to improve the noise performance of these pixels. However, focal plane arrays with small pixel pitch are constrained in terms of pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this brief the authors propose a novel approach to measure the residue outside the pixel using an analog-to-digital converter (ADC). A first prototype of the proposed pixel, in the form of a testbed, has been developed. It is aimed at medium-wave infrared imaging arrays that have a small pixel pitch. The prototype is composed of a pixel front end, a 12-bit successive approximation register ADC, a counter, and a comparator. The front end is a modified version of the conventional design and has been designed and fabricated in 90-nm CMOS, whereas off-the-shelf discrete components have been used to implement the ADC, comparator, and counter. A measured signal-to-noise ratio at low illumination levels is 55 dB.

A PFM based digital pixel with off-pixel residue measurement for 15μm pitch MWIR FPAs

Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge handling capability compared to their analog counterparts. Moreover, extended counting methods making use of leftover charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, medium wave infrared (MWIR) focal plane arrays (FPAs) having smaller pixel pitch are constrained in terms of pixel area which makes it difficult to add extended counting circuitry to the pixel. Thus, this paper investigates the performance of digital pixels employing off-pixel residue measurement. A circuit prototype of such a pixel has been designed for 15μm pixel pitch and fabricated in 90nm CMOS. The prototype is composed of a pixel front-end based on a PFM loop. The frontend is a modified version of conventional design providing a means for buffering the signal that needs to be converted to a digital value by an off-pixel ADC. The pixel has an integration phase and a residue measurement phase. Measured integration performance of the pixel has been reported in this paper for various detector currents and integration times.

Implementation of TDI based digital pixel ROIC with 15μm pixel pitch

A 15um pixel pitch digital pixel for LWIR time delay integration (TDI) applications is implemented which occupies one fourth of pixel area compared to previous digital TDI implementation. TDI is implemented on 8 pixels with oversampling rate of 2. ROIC provides 16 bits output with 8 bits of MSB and 8 bits of LSB. Pixel can store 75 M electrons with a quantization noise of 500 electrons. Digital pixel TDI implementation is advantageous over analog counterparts considering power consumption, chip area and signal-to-noise ratio. Digital pixel TDI ROIC is fabricated with 0.18um CMOS process. In digital pixel TDI implementation photocurrent is integrated on a capacitor in pixel and converted to digital data in pixel. This digital data triggers the summation counters which implements TDI addition. After all pixels in a row contribute, the summed data is divided to the number of TDI pixels(N) to have the actual output which is square root of N improved version of a single pixel output in terms of signal-to-noise-ratio (SNR).

Dynamic power reduction in digital pixel design for large format focal plane arrays

This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90 nm CMOS process with pixel pitch of 30 µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28 mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256×256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise.