Omer Ceylan

Design of a ROIC for Scanning Type HgCdTe LWIR Focal Plane Arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

Realization of a ROIC for 72x4 PV-IR detectors

Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1×4 and 72×4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons.

A fully digital readout employing extended counting method to achieve very low quantization noise

This paper presents a digital ROIC for staring type arrays with extending counting method to realize very low quantization noise while achieving a very high charge handling capacity. Current state of the art has shown that digital readouts with pulse frequency method can achieve charge handling capacities higher than 3Ge- with quantization noise higher than 1000e-. Even if the integration capacitance is reduced, it cannot be lower than 1-3 fF due to the parasitic capacitance of the comparator. For achieving a very low quantization noise of 200 electrons in a power efficient way, a new method based on measuring the time to measure the remaining charge on the integration capacitor is proposed. With this approach SNR of low flux pixels are significantly increased while large flux pixels can store electrons as high as 2.33Ge-. A prototype array of 32x32 pixels with 30μm pitch is implemented in 90nm CMOS process technology for verification. Simulation results are given for complete readout.

Implementation of pixel level digital TDI for scanning type LWIR FPAs

Implementation of a CMOS digital readout integrated circuit (DROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels with over sampling rate of 3. Analog signal integrated on integration capacitor is converted to digital domain in pixel, and digital data is transferred to TDI summation counters, where contributions of 8 pixels are added. Output data is 16 bit, where 8 bits are allocated for most significant bits and 8 bits for least significant bits. Control block of the ROIC, which is responsible of generating timing diagram for switches controlling the pixels and summation counters, is realized with VerilogHDL. Summation counters and parallel-to-serial converter to convert 16 bit parallel output data to single bit output are also realized with Verilog HDL. Synthesized verilog netlists are placed&routed and combined with analog under-pixel part of the design. Quantization noise of analog-to-digital conversion is less than 500e-. Since analog signal is converted to digital domain in-pixel, inaccuracies due to analog signal routing over large chip area is eliminated. ROIC is fabricated with 0.18μm CMOS process and chip area is 10mm2. Post-layout simulation results of the implemented design are presented. ROIC is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electron, while power consumption is less than 30mW. ROIC is designed to perform in cryogenic temperatures.

Design and realization of 144 x 7 TDI ROIC with hybrid integrated test structure

Design and realization of a 144x7 silicon readout integrated circuit (ROIC) based on switched capacitor TDI for MCT LWIR scanning type focal plane arrays (FPAs) and its corresponding hybrid integrated test circuits are presented. TDI operation with 7 detectors improves the SNR of the system by a factor of √7, while oversampling rate of 3 improves the spatial resolution of the system. ROIC supports bidirectional scan, 5 adjustable gain settings, bypass operation, automatic gain adjustment in case of mulfunctioning pixels and pixel select/deselect properties. Integration time of the system can be determined by the help of an external clock. Programming of ROIC can be done in parallel or serial mode according to the needs of the system. All properties except pixel select/deselect property can be performed in parallel mode, while pixel select/deselect property can be performed only in serial mode. ROIC can handle up to 3.75V dynamic range with a load of 25pF and output settling time of 80ns. Input referred noise of the ROIC is less than 750 rms electrons, while the power consumption is less than 100mW. To test ROIC in absence of detector array, a process and temperature compensated current reference array, which supplies uniform input current in range of 1-50nA to ROIC, is designed and measured both in room and cryogenic (77ºK) temperatures. Standard deviations of current reference arrays are measured 3.26% for 1nA and 0.99% for 50nA. ROIC and current reference array are fabricated seperately, and then flip-chip bonded for the test of the system. Flip-chip bonded system including ROIC and current reference test array is successfully measured both in room and cryogenic temperatures, and measurement results are presented. The manufacturing technology is 0.35μm, double poly-Si, four metal, 5V CMOS process.

Design of ROIC Based on Switched Capacitor TDI for MCT LWIR Focal Plane Arrays

Design and measurement of a silicon readout integrated circuit (ROIC) based on switched capacitor time delay integration (TDI) technique for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality for scanning type of detector by using switched capacitor technique with a supersampling rate of three, increasing SNR and the spatial resolution. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time, 5 gain settings at the input and auto gain adjustment with pixel deselection capability. Programming can be done parallel or serially with test mode functionality. ROIC can handle up to 3.75V dynamic range with the load being 25pF capacitive, output settling time is less than 80 nsec. This low power ROIC consumes less than 100mW. Moreover, input referred noise is less than 750 rms electrons. Simulations and measurements are done in both room temperature and cryogenic (77 °K) temperatures. In order to measure and simulate chip without a detector, process and temperature invariant current source block that imitate detector currents are designed as well. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process.

Physical device modeling of Si/Si1-xGex multi-quantum well detector to optimize Ge content for higher thermal sensitivity

This paper presents the physical device modeling of a Si/Si1-xGex multi-quantum well (MQW) detector to optimize the Ge content in the Si/Si1-xGex well required to enhance thermal sensitivity for a potential microbolometer application. The modeling approach comprises a self-consistent coupled Poisson-Schroedinger solution in series with the thermionic emission theory at the Si/Si1-xGex heterointerface and quantum confinement within the Si/Si1-xGex MQW. The integrated simulation environment developed in Sentauruas WorkBench (SWB) TCAD is employed to investigate the transfer characteristics of the device consisting three stacks of Si/Si1-xGex wells with an active area of 17μm x 17μm were investigated and compared with experiment data.

Highly efficient MIM diodes for NIR and SWIR applications

Metal-insulator-metal (MIM) diodes are highly considered in high frequency applications in form of rectennas for energy harvesting applications due to their fast speed, small size, and ease of fabrication and IC compatibility. In these diodes, insulators are integral part of the device, determining performance parameters. In this study, we have evaluated HfO2 and Al2O3 based MIM diode structures to compare and determine performance parameters, with conversion efficiency being prioritized. The fabrication processes in physical vapor deposition (PVD) systems for the MIM diodes resulted in the devices having high non-linearity and responsivity. Also, to achieve uniform and very thin insulator layer atomic layer deposition (ALD) was used. We implemented the same MIM structure in 10x10 array form, with active area of 200x325 nm2. The efficiency values of same arrays tested with 1200 and 1600 nm wavelength LEDs for 200x325 nm2 diode active area without applying bias. The conversion efficiency value of the HfO2 based structures calculated as 5% for 1200 nm wavelength. These measured values of conversion efficiency are reported for the first time in the literature for MIM diodes in SWIR operation.

A low-power CMOS readout IC with on-chip column-parallel SAR ADCs for microbolometer applications

A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (~1M Ω) and higher TCR values (~%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17x17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process.

A low-power CMOS readout IC design for bolometer applications

A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.