Mark P. van der Heijden

A compact 12-watt high-efficiency 2.1-2.7 GHz class-E GaN HEMT power amplifier for base stations

A compact broadband class-E power amplifier design is presented. High broadband power efficiency is observed from 2.0–2.5 GHz, where drain efficiency ≫74% and PAE ≫71%, when using 2nd-harmonic input tuning. The highest in-band efficiency performance is observed at 2.14 GHz from a 40V supply with peak drain-efficiency of 77.3% and peak PAE of 74.0% at 12W output power and 14dB gain. The best broadband output power performance is observed from 2.1–2.7 GHz without 2nd-harmonic input tuning, where the output power variation is within 1.5dB and power efficiency is between 53% and 66%.

A 19W high-efficiency wide-band CMOS-GaN class-E Chireix RF outphasing power amplifier

A class-E Chireix outphasing power amplifier is presented that enables high efficiency across a wide power back-off range and RF bandwidth. In this design the Chireix compensation elements and class-E loading conditions are provided by an asymmetric coupled-line power combiner. The class-E operated GaN HEMT switches are driven by high-speed, high-voltage CMOS drivers, implemented in a standard 65nm process technology. The proposed concept demonstrates 51.6% system average power efficiency and 65.1% average drain efficiency for a 7.5dB PAR WCDMA signal at 1.95GHz, while meeting the ACLR specifications. Moreover, the PA demonstrated more than 60% drain efficiency across a 6dB power back-off range and up to 19W peak power between 1800–2050MHz.

A Package-Integrated Chireix Outphasing RF Switch-Mode High-Power Amplifier

This paper describes the design and implementation of a package-integrated Chireix outphasing RF switch-mode power amplifier (PA). The optimum loading conditions, based on class E, and the Chireix compensation elements are provided to the active devices by a dedicated low-loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieved 70.6-W peak power with 73% peak drain efficiency at 2.3 GHz and 28 V, and up to 81% peak drain efficiency at 2.2 GHz and 20 V. When operated for maximum power at 28 V, it reached 53.5%/43.5% average drain/total efficiency for a 9.6-dB peak-to-average-power-ratio W-CDMA signal at 2.3 GHz with low ACLR1/2 levels ( -49/ -56 dBc after memoryless digital predistortion). Moreover, from 2.1 to 2.4 GHz, the realized PA demonstrated more than 50% drain efficiency across > 260, > 160, and > 80 MHz at 6-, 8-, and 10-dB back-off, respectively.

A 65nm CMOS pulse-width-controlled driver with 8V pp output voltage for switch-mode RF PAs up to 3.6GHz

State-of-the-art wireless communication radios are implemented in deep-submi-cron CMOS, including the RF power amplifiers (PAs). However, in wireless infrastructure systems, the RF PA is often realized in an LDMOS or a compound technology to obtain the required large output powers. For next-generation reconfigurable infrastructure systems, the switch-mode PAs (SMPA) seem to offer the required flexibility for multiband multimode transmitters. In order to interface the high-power devices of the SMPA with the digital CMOS blocks of the transmitter, a wideband RF CMOS driver capable to generate high voltage (HV) swings is required. In this way, digital signal processing can be directly applied to control the required input pulse shapes of the SMPA.

A 70W package-integrated class-E Chireix outphasing RF power amplifier

A high-power class-E Chireix outphasing RF power amplifier integrated inside a transistor package is described. The optimum class-E loading conditions and the Chireix compensation elements are provided to the active devices by a dedicated ultra-low loss bondwire-based transformer power combiner that enables a very small form factor and low cost. The realized prototype achieves 70.6 W peak power with 73% peak drain-efficiency at 2.3 GHz, and up to 81% peak drain-efficiency for slightly lower power at 2.2 GHz. When operated for maximum power, it reaches 53.5%/43.5% average drain-/total-efficiency for a 9.6 dB PAR W-CDMA signal at 2.3 GHz with low ACLR1/2 levels (-49/-56 dBc after memory-less DPD).

High efficiency RF pulse width modulation with tunable load network class-E PA

In this paper, a 10 W peak power 2 GHz highly efficient RF pulse width modulation (RF-PWM) based transmitter is presented. RF-PWM signals are generated with a dedicated 65 nm CMOS modulator and subsequently amplified with a GaN Class-E power amplifier (PA). The modulator use extended drain MOS (EDMOS) high voltage transistors to provide the required voltage swing to drive the GaN used as a switch. The imaginary load impedance of the Class-E is electronically tunable and is implemented with in-house high breakdown voltage SiC varactors. The tunable imaginary load impedance enables optimization of the Class-E versus the duty cycle (pulse width). The peak efficiency is therefore preserved over a wide range of output power levels. The measured drain efficiency of the Class-E output stage is above 70% over a 6.5 dB output power dynamic range. The overall transmitter efficiency is above 60% for the same dynamic range.

A radio-frequency reconfigurable CMOS-GaN class-E Chireix power amplifier

A new load-insensitive class-E power amplifier mode is presented that that enables frequency reconfigurability by statically changing the switch duty-cycle without compromising its tuned efficiency performance. The technique is tested on a prototype CMOS-GaN class-E Chireix power amplifier designed for 1.8-2.2 GHz. The drain efficiency is more than 55% at 8dB back-off and more than 60% at 6dB back-off across the band by reconfiguring the duty-cycle at each frequency via the pulse-width controlled CMOS drivers.

0.75 Watt and 5 Watt drivers in standard 65nm CMOS technology for high power RF applications

In this paper, we present two high voltage (up to 10V supply voltage), RF drivers in standard 65nm CMOS technology. The medium power (MP) driver operates from 0.5GHz to 4GHz with up to 9.6V peak-to-peak(pp) output voltage swing while driving a 3pF load capacitance. This driver consumes 0.75W dc power at 2GHz and achieves a duty-cycle control of 23% to 82% at 1GHz and 38% to 73% at 2GHz. The high power (HP) driver consumes 5W dc power at 2.14GHz while driving an RF power device (50W) with ≈30pF input capacitance. The CMOS drivers can serve as key building block for next-generation reconfigurable multiband multimode transmitters for wireless infrastructure systems, interfacing digital CMOS circuitry with high-power transistors.

Efficient LDMOS device operation for envelope tracking amplifiers through second harmonic manipulation

In this work efficient LDMOS device operation for envelope tracking amplifier systems is discussed. Utilizing the voltage dependence of Cds in combination with a well chosen 2nd harmonic output termination, a “hybrid” combination of class-J* and class-B device operation is defined, which yields improved efficiency at low supply voltages in power back-off, while avoiding device breakdown when operating at high supply voltages. Using these techniques with a Gen7 NXP 2W LDMOS device in a load-pull test bench, more than 63% drain efficiency over a 10 dB power back-off range is achieved at 2.14 GHz. The proposed method is supported by simulations and measurements and is directly applicable to envelope tracking power amplifiers.

Scalable CMOS power devices with 70% PAE and 1, 2 and 3.4 Watt output power at 2GHz

This paper reports RF power devices achieving 70% power-added efficiency (PAE) with 1, 2 and 3.4W output power at 2GHz. The power devices operate as sub-optimum class-E power amplifiers, having the advantage of 1.6 times higher output power with a slightly lower PAE than conventional class-E. The power devices use high voltage extended-drain NMOS (ED-NMOS) transistors in standard 65nm CMOS. A scalable layout design that we used preserves the high PAE for the various output power levels.