Jan Sophia Vromans
NXP Semiconductors
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Publication
Featured researches published by Jan Sophia Vromans.
international microwave symposium | 2009
Mark P. van der Heijden; Mustafa Acar; Jan Sophia Vromans
A compact broadband class-E power amplifier design is presented. High broadband power efficiency is observed from 2.0–2.5 GHz, where drain efficiency ≫74% and PAE ≫71%, when using 2nd-harmonic input tuning. The highest in-band efficiency performance is observed at 2.14 GHz from a 40V supply with peak drain-efficiency of 77.3% and peak PAE of 74.0% at 12W output power and 14dB gain. The best broadband output power performance is observed from 2.1–2.7 GHz without 2nd-harmonic input tuning, where the output power variation is within 1.5dB and power efficiency is between 53% and 66%.
international microwave symposium | 2011
Mark P. van der Heijden; Mustafa Acar; Jan Sophia Vromans; David A. Calvillo-Cortes
A class-E Chireix outphasing power amplifier is presented that enables high efficiency across a wide power back-off range and RF bandwidth. In this design the Chireix compensation elements and class-E loading conditions are provided by an asymmetric coupled-line power combiner. The class-E operated GaN HEMT switches are driven by high-speed, high-voltage CMOS drivers, implemented in a standard 65nm process technology. The proposed concept demonstrates 51.6% system average power efficiency and 65.1% average drain efficiency for a 7.5dB PAR WCDMA signal at 1.95GHz, while meeting the ACLR specifications. Moreover, the PA demonstrated more than 60% drain efficiency across a 6dB power back-off range and up to 19W peak power between 1800–2050MHz.
radio frequency integrated circuits symposium | 2009
Mustafa Acar; Mark P. van der Heijden; Iouri Volokhine; Melina Apostolidou; Jan Sonsky; Jan Sophia Vromans
This paper reports RF power devices achieving 70% power-added efficiency (PAE) with 1, 2 and 3.4W output power at 2GHz. The power devices operate as sub-optimum class-E power amplifiers, having the advantage of 1.6 times higher output power with a slightly lower PAE than conventional class-E. The power devices use high voltage extended-drain NMOS (ED-NMOS) transistors in standard 65nm CMOS. A scalable layout design that we used preserves the high PAE for the various output power levels.
Archive | 2009
Mark P. van der Heijden; Antonius Johannes Matheus de Graaw; Jan Sophia Vromans; Rik Jos
Archive | 2011
Mark van der Heijden; Mustafa Acar; Jan Sophia Vromans; Melina Apostolidou
Archive | 2010
Mark P. van der Heijden; Mustafa Acar; Jan Sophia Vromans
Archive | 2009
Mark P. van der Heijden; Mustafa Acar; Jan Sophia Vromans; Melina Apostolidou
Archive | 2010
Jan Sophia Vromans; Mark P. van der Heijden; Mustafa Acar
Archive | 2010
Jan Sophia Vromans; Mark P. van der Heijden; Mustafa Acar
Archive | 2011
Der Heijden Mark Pieter Van; Mustafa Acar; Jan Sophia Vromans; Melina Apostolidou