Meng-Hsiung Hung

Dual-band integrated Wi-Fi PAs with load-line adjustment and phase compensated power detector

A load-line adjusted 2.4GHz PA is designed to operate in full power (18dBm/150mA) & mid power (7dBm/19mA) in OFDM with ~130mA saving. To improve network throughput in dense environment with per-packet TX power control, the phase-compensated power detector achieves ±0.6dB accuracy for the entire 5GHz band over 2:1 VSWR and 16dBm±0.25dB over channel flatness in VHT80MCS9. The chip area is 0.21mm2 for load-line adjusted 2.4GHz PA and 0.13 mm2 for 5GHz PA with power detector.

A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC

This paper describes a dual-band 802.11abgn/ac compliant transceiver in a 4-in-l combo connectivity SoC. It integrates the PAs, LNAs, T/R switches, and the 5GHz Balun. Due to the transmitter architecture and adaptive biasing scheme both are tailored for wide bandwidth, the 5GHz transmitter achieves 18.2dBm average output power for 802.11ac VHT80 MCS9 (Modulation and Coding Scheme 9). Within the 80MHz channel bandwidth, the IQ mismatch becomes frequency dependent, and is compensated through calibration. In the 2.4GHz transmitter, its PA load-line is adjustable. The power efficiency is thus remained similarly regardless the output power is at 20dBm for long range operation, or 8dBm for short range operation. By controlling the turn-on resistance of power island switch in digital baseband, and properly sizing the filler cap, the switching noise can be well controlled. The chip occupies 24.9mm2 in 55nm 1P6M CMOS technology, where 1.3mm2 is for 5GHz WLAN and 2.1mm2 is for 2.4GHz WLAN/BT.

A 0.27mm 2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS

An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.

A 55nm CMOS 4-in-1 (11b/g/n, BT, FM, and GPS) radio-in-a-package with IPD front-end components directly connected to antenna

This paper presents a 55nm 4-in-1 (11b/g/n, BT, FM, and GPS) radio assembled side-by-side with a 3-metal layer integrated-passive-device (IPD) chip in a QFN40 package. One 2.4GHz transceiver is area-efficiently shared between WiFi and Bluetooth systems. Including a 3dB IPD insertion loss, at chip output (antenna port) the saturated output power of the 11bgn integrated PA is 25dBm; the receiver noise figure is 6dB and 7dB in WiFi and BT modes, respectively. The shared synthesizer locks to within 4ppm target frequency during WiFi/BT channel switching in less than 23 usec. Tracking sensitivity of the GPS receiver and the sensitivity of the FM receiver (including IPD loss) are -162dBm and 2.7dBuVrms, respectively. The IPD chip contains a 2.4GHz WiFi/BT balanced tri-section filter and matching network; a 2.4GHz/1.6GHz diplexer; and a GPS 5th order elliptical filter and its matching network. The radio and IPD die sizes are 3.4mm2 and 3.1mm2, respectively.