Robert Bogdan Staszewski

Chapter 2 – Millimeter-Wave Frequency Synthesizers

This chapter reviews the basics of frequency synthesizer design. It begins with an introduction to frequency synthesizer fundamentals in Section 2.1. The operation of both analog and all-digital phase-locked loops is presented in Section 2.2. Section 2.3 compares two frequency synthesizer topologies that are most commonly employed for mm-wave frequency generation: phase-locked loop (PLL) with a fundamental oscillator and PLL-based harmonic generation. Both of the synthesizer topologies can be made digitally intensive using the architecture and digital techniques that will be described in Chapters 4–8.

Chapter 3 – Circuit Design Techniques for mm-Wave Frequency Synthesizer

This chapter reviews the circuit design techniques for mm-wave PLLs, which can be applied to both analog- and digitally intensive PLLs. A low phase noise, wideband oscillator is one of the most challenging and critical building blocks in a PLL. It dominates the synthesizer’s RF performance beyond the closed-loop bandwidth of the PLL. A frequency divider chain scales the mm-wave carrier down in frequency to be able to compare its phase with a frequency reference at a lower rate. The divider chain normally consumes considerable power (e.g., 30% of the total power consumption in a mm-wave PLL) and operates across a large frequency range. Several commonly used divider topologies are compared in Section 3.2. Section 3.3 describes frequency multiplier design, which is widely used to further extend the PLL operating frequency (e.g., to above 100xa0GHz).

Digital Techniques for Higher RF Performance

This chapter focuses on digital calibration techniques intimately involved with the modulating ADPLL, including DCO gain calibration, multibank DCO gain linearization, tuning step mismatch calibration and compensation, and synchronization for a multirate system. These calibration algorithms are the key to obtaining superior RF performance, especially for frequency synthesizers operating in mm-wave bands. The digitally intensive architecture facilitates these calibration techniques, which is a major strength of an ADPLL over conventional charge-pump PLLs.

Application: A 60-GHz All-Digital PLL for FMCW Transmitter Applications

This chapter describes a millimeter (mm)-wave all-digital PLL (ADPLL) design example for a 60-GHz FMCW radar application. The multi-rate ADPLL-based frequency modulator architecture provides wideband frequency modulation capability, which can be used for many mm-wave applications. The implementation details of the key circuit building blocks that are described in this chapter include the DCO interface, frequency divider chain, TDC design and calibration, frequency reference slicer, and phase error glitch removal. In addition, the top-level floor plan considerations for a mm-wave ADPLL are also highlighted in this chapter.

Chapter 5 – Millimeter-Wave Digitally Controlled Oscillator

This chapter describes a high-performance digitally controlled oscillator (DCO) design at millimeter (mm)-wave frequencies. Section 5.1 reviews DCO design at single-gigahertz frequencies. Although most of the design methodologies can be applied to mm-wave DCOs, new digital tuning techniques contribute to knowledge on how to achieve sub-megahertz frequency resolution and wide tuning range simultaneously in the mm-wave bands. These digital tuning techniques are elaborated on in Sections 5.2 and 5.3. Section 5.2 introduces a digitally reconfigurable resonator comprised of switched metal capacitors distributed across the resonator to tune the oscillation frequency. Section 5.3 describes two tuning step attenuation techniques in order to obtain sub-megahertz frequency resolution. Two 60-GHz DCO design examples (implemented in 90-nm CMOS) are discussed in Section 5.4.

Chapter 8 – Design for Test of the mm-Wave ADPLL

The advantages of on-chip debugging and characterization capabilities of critical RF performance are myriad in SoC applications. This chapter focuses on design-for-test (DFT) and design-for-characterization (DFC) techniques applied to an ADPLL targeting mm-wave frequency. System snapshotting via an on-chip SRAM is a powerful method of accurately identifying the root causes of any design deficiencies. More importantly, it offers the possibility of self-healing (i.e., detecting the performance degradation or defects, and then reconfiguring certain design parameters to automatically regain the normal performance). Moreover, low-cost, built-in self-test (BIST), and self-characterization (BISC) of PLL performance, including critical building blocks (e.g., digitally controlled oscillator) are introduced. The on-chip RF characterization capability enhances test coverage, and reduces test time and production costs. The DFT and DFC techniques are integrated and benchmarked using a 60-GHz ADPLL-based transmitter in 65-nm CMOS.